Two-Level Texture Cache Architecture for Bandwidth and Power Efficiency

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Solution Overview

Problem

Conventional texture caching approaches in graphics systems face limitations in memory efficiency and bandwidth usage due to fixed compression formats, leading to inefficiencies in texture data access and decompression processes.

Innovation Solution

A texture cache architecture that includes a Level 0 cache for uncompressed data and a Level 1 cache for compressed data, with streaming FIFOs for buffering and decompression, allowing for efficient reuse of decompressed data and reduced power consumption by minimizing unnecessary decompression and memory access.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If compressed texture data is stored in a single cache level, then memory bandwidth is reduced, but decompression power consumption increases due to repeated decompression operations

Engineering Contradiction:
Improvememory bandwidthVSAvoiddecompression power consumption
Core Design Contradiction:
Loss of energyVSUse of energy by moving object

Solution Approach 1:

The patent divides the texture cache into two distinct levels: a first cache storing compressed texture data and a second cache storing decompressed texture data. This segmentation allows the system to reduce memory bandwidth by keeping compressed data in the first cache while enabling power-efficient access to decompressed data in the second cache, avoiding repeated decompression operations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs decompression in advance by storing decompressed texture data in the second cache before it is needed for rendering. This preliminary action allows subsequent access to use the already-decompressed data from the second cache, reducing both memory bandwidth requirements and decompression power consumption.

Inventive Principle:
Principle #10Preliminary action

2Use of energy by moving object

If a two-level cache architecture is implemented, then decompression power is reduced, but device complexity increases

Engineering Contradiction:
Improvedecompression powerVSAvoidcache architecture complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent combines the first cache and second cache into a unified texture cache device with shared control logic and memory management. This merging approach reduces device complexity by consolidating control functions while maintaining the benefits of having both compressed and decompressed data storage levels.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The texture cache device is designed to perform multiple functions: storing compressed data, storing decompressed data, managing decompression operations, and serving different data requests. This multi-functionality is achieved through a unified architecture that handles both cache levels and decompression tasks within a single device, reducing overall system complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Ease of manufacture

If fixed compression formats are used, then implementation is simpler, but adaptability to different texture sizes is reduced

Engineering Contradiction:
Improveimplementation simplicityVSAvoidtexture size adaptability
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent implements a dynamic compression system where the compression format and block size can be adjusted based on the specific texture data being processed. The system can adaptively choose between different compression schemes and block dimensions, allowing it to handle various texture sizes and patterns efficiently while maintaining implementation feasibility through structured control logic.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10181176B2Efficient low-power texture cache architecture
Publication Date: 2019.01.15 SAMSUNG ELECTRONICS CO LTD
  • US10181176B2 patent drawing
  • US10181176B2 patent drawing
  • US10181176B2 patent drawing

AI summary

A texture cache architecture includes a first texture cache to store compressed texel data and a second texture cache to store decompressed texel data. A controller schedules accesses to access texel data from the first or second texture cache. The second texture cache permits decompressed texel data to be reused for more than one texel access request.