Non-blocking Texture Cache Retry Buffer for In-order Completion

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Solution Overview

Problem

Texture mapping systems using out-of-order completion processes face issues during alpha blending and multi-texturing processes, requiring in-order completion to maintain stability and performance, while existing non-blocking caches may introduce overhead and constraints.

Innovation Solution

A non-blocking texture cache memory is designed with a retry buffer, lookup unit, verification unit, and output control unit to handle cache hits and misses efficiently, dividing the pipeline into hit and miss processes to ensure in-order completion without stalling, using a retry buffer to store and output result data and a cache miss processing unit to collect data from external memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If out-of-order completion process is used in texture mapping, then processing speed is improved, but stability deteriorates during alpha blending and multi-texturing processes

Engineering Contradiction:
Improveprocessing speedVSAvoidstability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The texture cache memory is divided into multiple independent pipelines (first pipeline for cache hits, second pipeline for cache misses). Each pipeline processes texture requests independently, allowing out-of-order completion within each pipeline while maintaining overall system stability through structured separation of processing paths.

Inventive Principle:
Principle #1Segmentation

2Reliability

If in-order completion process is used, then stability is improved, but processing speed deteriorates due to sequential processing requirements

Engineering Contradiction:
ImprovestabilityVSAvoidprocessing speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The system dynamically selects between in-order and out-of-order processing based on the pipeline type. The first pipeline (cache hits) uses out-of-order completion for speed, while the second pipeline (cache misses) uses in-order completion for stability. This dynamic adaptation allows the system to optimize for both speed and stability in different contexts.

Inventive Principle:
Principle #15Dynamics

3Productivity

If non-blocking cache is used, then productivity is improved, but device complexity increases due to retry buffer and verification mechanisms

Engineering Contradiction:
ImproveproductivityVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The non-blocking cache is segmented into multiple pipelines with dedicated retry buffers and verification units for each. This segmentation allows the complexity to be distributed and managed independently, where each pipeline handles specific cache scenarios (hits or misses) with appropriate retry mechanisms, improving overall productivity without overwhelming complexity.

Inventive Principle:
Principle #1Segmentation

4Reliability

If retry operations are implemented in texture cache, then reliability is improved, but performance degradation occurs due to additional processing overhead

Engineering Contradiction:
ImprovereliabilityVSAvoidperformance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The verification unit checks whether texture data is already present in the retry buffer before initiating retry operations. This preliminary check prevents unnecessary retry processing, thereby maintaining reliability by ensuring data correctness while avoiding performance degradation from redundant operations. The system performs the verification action in advance to optimize the retry process.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9727474B2Texture cache memory system of non-blocking for texture mapping pipeline and operation method of texture cache memory
Publication Date: 2017.08.08 SAMSUNG ELECTRONICS CO LTD
  • US9727474B2 patent drawing
  • US9727474B2 patent drawing
  • US9727474B2 patent drawing

AI summary

A non-blocking texture cache memory for a texture mapping pipeline and an operation method of the non-blocking texture cache memory may include: a retry buffer configured to temporarily store result data according to a hit pipeline or a miss pipeline; a retry buffer lookup unit configured to look up the retry buffer in response to a texture request transferred from a processor; a verification unit configured to verify whether result data corresponding to the texture request is stored in the retry buffer as the lookup result; and an output control unit configured to output the stored result data to the processor when the result data corresponding to the texture request is stored as the verification result.