Texture Cache Sector Fetching to Reduce GPU Memory Bandwidth

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Solution Overview

Problem

Cache misses in texture caches for graphics processing units (GPUs) result in significant memory bandwidth consumption and limited power savings due to the need to fetch entire cache lines, even when only a portion of the data is required, leading to inefficient use of resources.

Innovation Solution

Partition cache lines into sectors and selectively generate miss requests for subsets of cache lines based on heuristics such as temporal and spatial locality, color/depth compression, and predicted access patterns to optimize memory access and reduce power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If entire cache lines are fetched on cache miss, then complete data is available for processing, but memory bandwidth consumption increases and power savings are limited

Engineering Contradiction:
Improvedata completenessVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The cache line is divided into multiple sectors, and the system selectively fetches only the specific sector that contains the requested data rather than the entire cache line. This segmentation allows the GPU to retrieve minimal necessary data, reducing memory bandwidth consumption and power usage while maintaining data completeness for the specific access request.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system extracts and fetches only the specific sector containing the requested data from the cache line, eliminating the need to transfer unnecessary data. This extraction approach reduces the volume of data transferred over memory bandwidth while ensuring the complete necessary data is still retrieved for processing.

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If entire cache lines are fetched on cache miss, then all potential data is available, but memory bandwidth is consumed inefficiently

Engineering Contradiction:
Improvedata availabilityVSAvoidmemory bandwidth efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

By segmenting the cache line into sectors and selectively fetching only the required sector, the system improves memory bandwidth efficiency. The segmentation enables precise targeting of necessary data, preventing wasteful consumption of memory bandwidth on unnecessary data transfer while ensuring complete availability of the specific data needed for the current processing operation.

Inventive Principle:
Principle #1Segmentation

3Loss of energy

If selective sector fetching is implemented, then memory bandwidth is conserved, but cache hit rate may decrease due to partial cache line updates

Engineering Contradiction:
Improvememory bandwidth consumptionVSAvoidcache hit rate
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The system performs preliminary analysis of the access pattern to determine whether selective sector fetching should be applied. By predicting future access patterns and pre-determining the optimal fetch strategy, the system can maintain higher cache hit rates while still conserving memory bandwidth, as the preliminary analysis allows for intelligent decision-making about data retrieval strategies.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system uses feedback from access patterns to dynamically adjust the cache fetch strategy. By monitoring whether selective sector fetching is successful and adjusting behavior based on observed performance, the system can maintain or improve cache hit rates while continuing to conserve memory bandwidth through selective data retrieval.

Inventive Principle:
Principle #23Feedback

Data Source

PatentEP4268178B1Selective generation of miss requests for cache lines
Publication Date: 2025.10.29 ADVANCED MICRO DEVICES INC
  • EP4268178B1 patent drawingFigure 1
  • EP4268178B1 patent drawingFigure 2
  • EP4268178B1 patent drawingFigure 3

AI summary

A graphics pipeline [200] includes a texture cache [207] having cache lines [300, 305] that are partitioned into a plurality of subsets. The graphics pipeline also includes one or more compute units [121, 122, 123] that selectively generates a miss request for a first subset of the plurality of subsets of a cache line in the texture cache in response to a cache miss for a memory access request to an address associated with the first subset of the cache line. In some embodiments, the cache lines are partitioned into a first sector and a second sector. The compute units generate miss requests for the first sector, and bypass generating miss requests for the second sector, in response to cache misses for memory access requests received during a request cycle being in the first sector.