Texture Cache Coherency via View Hashing
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Solution Overview
Problem
Multiple views of a surface texture in texture processing hardware cause cache coherency and consistency issues, leading to increased cache misses and power consumption due to the need to invalidate all cache lines when data is written, which reduces cache performance.
Innovation Solution
A method that uses hash values associated with texture headers to determine potential aliasing between views, allowing only aliased cache entries to be invalidated, maintaining cache coherency and reducing unnecessary cache misses and system memory fetches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all cache lines are invalidated when data is written to any cache line, then cache coherency is maintained, but cache performance deteriorates and power consumption increases
Solution Approach 1:
The patent segments the cache invalidation process by introducing view-specific cache entries and view identifiers. Instead of invalidating all cache lines uniformly, the system divides cache management into view-specific segments, allowing selective invalidation based on which view generated the write operation. This segmentation enables maintaining coherency for only the relevant view's cache entries rather than all cache lines.
Solution Approach 2:
The patent applies local quality by making cache coherency enforcement localized to specific views rather than applying it globally to all views. Each view has its own cache entries tagged with view identifiers, and invalidation operations are scoped to affect only the local view's cache entries. This localized approach maintains coherency where needed while avoiding unnecessary invalidations in other views.
2Reliability
If all cache lines are invalidated when data is written, then cache coherency is maintained, but power consumption increases
Solution Approach 1:
The patent segments the cache invalidation process by introducing view-specific cache entries and view identifiers. Instead of invalidating all cache lines uniformly, the system divides cache management into view-specific segments, allowing selective invalidation based on which view generated the write operation. This segmentation enables maintaining coherency for only the relevant view's cache entries rather than all cache lines.
Solution Approach 2:
The patent applies partial action by performing invalidation only on the subset of cache entries that are actually affected by a write operation, rather than invalidating all cache lines. By using view identifiers to determine which cache entries belong to the writing view, the system performs just enough invalidation to maintain coherency without the excessive action of clearing the entire cache, thereby reducing power consumption.
3Adaptability or versatility
If multiple views of a surface texture are simultaneously active, then texture processing flexibility is improved, but cache coherency problems arise
Solution Approach 1:
The patent segments cache management by view by introducing view identifiers that are associated with each cache entry. This segmentation allows multiple views to simultaneously access the texture cache without interfering with each other's coherency. Each view's cache entries are independently tracked and invalidated only when that specific view performs write operations, enabling flexible multi-view processing while maintaining reliability.
Solution Approach 2:
The patent introduces view identifiers as an intermediary mechanism that mediates between multiple views and the cache coherence protocol. These identifiers act as a intermediary layer that tracks which cache entries belong to which view, enabling the system to maintain coherency for each view independently while allowing simultaneous active views. This intermediary mechanism resolves the conflict between multi-view flexibility and cache coherency reliability.
Data Source
AI summary
Techniques are disclosed for performing memory access operations. A texture unit receives a memory access operation that includes a tuple associated with a first view in a plurality of views. The texture unit retrieves a first hash value associated with a first texture header in a plurality of texture headers, where the first texture header is related to the first view. The texture unit retrieves a second hash value associated with a second texture header in the plurality of texture headers, where the second texture header is related to a second view. The texture unit determines whether the first view is potentially aliased with the second view, based on the first and second hash values. If so, then the texture unit invalidates a cache entry in a cache memory associated with the second texture header. Otherwise, the texture unit maintains the cache entry.