Hardware Texture Filtering Unit Fixed-Point Conversion
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Solution Overview
Problem
Current texture filtering methods in 3D computer graphics are computationally expensive and prone to rounding errors, leading to visual artefacts in rendered scenes due to intermediate rounding steps in floating-point modules.
Innovation Solution
A texture filtering unit implemented in hardware that converts input texture values from floating-point to fixed-point representation, generates a single composite filter coefficient, and performs multiplication and addition operations without intermediate rounding, ensuring fully accurate outputs with high throughput and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If floating-point modules with intermediate rounding steps are used for texture filtering, then the filtering can be performed with standard hardware, but rounding errors occur leading to visual artefacts
Solution Approach 1:
The patent changes the numerical representation parameter from floating-point to fixed-point format for intermediate calculations. This parameter change eliminates rounding errors during intermediate steps while maintaining compatibility with standard hardware arithmetic units, thereby improving filtering accuracy without introducing visual artefacts.
2Adaptability or versatility
If multiple filter coefficients are used for different filtering methods, then versatile filtering options are available, but the hardware complexity increases
Solution Approach 1:
The patent merges multiple filter coefficients into a single composite filter coefficient that encapsulates the effects of multiple filtering methods. This consolidation reduces the number of separate coefficient storage units and selection logic required, thereby reducing hardware complexity while maintaining versatility through the composite coefficient's ability to represent different filtering approaches.
Solution Approach 2:
The single composite filter coefficient is designed to serve multiple filtering methods universally. By encoding information from volumetric, anisotropic, and trilinear filtering into one coefficient structure, the hardware can perform various filtering operations without requiring separate dedicated coefficient sets for each method, thus reducing overall device complexity.
3Productivity
If traditional texture filtering hardware is implemented, then the functionality is provided, but power consumption is high and area efficiency is low
Solution Approach 1:
The patent extracts and eliminates redundant control logic and intermediate rounding operations from traditional texture filtering hardware. By removing these unnecessary components and steps, the design reduces power consumption and hardware area while preserving the essential filtering functionality and maintaining high throughput capability.
4Ease of operation
If intermediate rounding steps are performed in floating-point modules, then standard floating-point arithmetic can be used, but filtering accuracy deteriorates
Solution Approach 1:
The patent changes the arithmetic operation parameter from floating-point with rounding to fixed-point arithmetic. This change eliminates intermediate rounding steps that degrade precision, allowing the system to maintain high filtering accuracy while still using standard hardware arithmetic units that can efficiently handle fixed-point calculations.
Data Source
AI summary
A texture filtering unit has inputs arranged to receive at least two texture values each clock cycle and a plurality of filter coefficients, the plurality of filter coefficients relating to a plurality of different texture filtering methods; hardware logic arranged to convert the input texture values to fixed-point representation; a coefficient merging logic block arranged to generate a single composite filter coefficient for each input texture value from the plurality of filter coefficients; one multiplier for each input texture value, wherein each multiplier is arranged to multiply one of the input texture values by its corresponding single composite filter coefficient; an addition unit arranged to add together outputs from each of the multipliers; hardware logic arranged to convert an output from the addition unit back to floating-point format; and an output arranged to output the converted output from the addition unit.