Texture Mapping Cache Memory Segmentation for Access Speed

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Solution Overview

Problem

Current 3D graphic rendering processes face inefficiencies in accessing texture data from cache memory, leading to delays and increased data bandwidth requirements, as existing methods do not effectively utilize cache memory resources to improve processing speed.

Innovation Solution

Implementing an apparatus with odd and even numbered index cache memories, where texture data is stored in blocks based on address indexes, allowing for parallel read requests to be generated between the two cache types to optimize access speed without increasing cache memory size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a single cache memory is used to store texture data, then the cache memory size is reduced, but the access speed is limited due to sequential reading requirements

Engineering Contradiction:
Improvetexture data access speedVSAvoidcache memory structure complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The cache memory is segmented into multiple independent cache memories (first cache memory and second cache memory), each capable of storing and providing texture data independently. This segmentation allows parallel reading operations to occur simultaneously from both cache memories, thereby improving the overall access speed for texture data without requiring a single large complex cache structure.

Inventive Principle:
Principle #1Segmentation

2Productivity

If texture data is read from main memory, then the data bandwidth requirement is reduced, but the processing speed is delayed

Engineering Contradiction:
Improvetexture mapping processing speedVSAvoiddata bandwidth requirement
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

Texture data is pre-loaded and stored in the cache memories before being needed for texture mapping. By performing the action of storing frequently accessed texture data in advance within the cache memory structure, the system eliminates the need to read from main memory during the critical texture mapping process, thereby improving processing speed without significantly increasing data bandwidth requirements.

Inventive Principle:
Principle #10Preliminary action

3Speed

If a larger cache memory is used to store all texture data, then the access speed is improved, but the memory size and resource consumption increase

Engineering Contradiction:
Improvetexture data read speedVSAvoidcache memory size
Core Design Contradiction:
SpeedVSVolume of stationary object

Solution Approach 1:

Instead of using a single large cache memory, the system divides the caching function into multiple smaller cache memories. Each cache memory stores a portion of the texture data, and the controller manages which cache memory to access based on the required texture data. This approach achieves fast access speeds while keeping each individual cache memory size manageable and reducing overall resource consumption.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system introduces an additional dimension of organization by using multiple cache memories with different storage locations and access paths. Rather than expanding a single cache memory in one dimension, the system adds another dimension of parallelism through multiple cache memory instances, allowing simultaneous access from different locations without proportionally increasing the total memory volume required.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS8605101B2Apparatus and method of reading texture data for texture mapping
Publication Date: 2013.12.10 SAMSUNG ELECTRONICS CO LTD
  • US8605101B2 patent drawing
  • US8605101B2 patent drawing
  • US8605101B2 patent drawing

AI summary

An apparatus and method of reading texture data for texture mapping. Each of a plurality of blocks included in a cache memory may have any one of an even numbered index or odd numbered index. In this instance, the cache memory may be embodied with an odd numbered index cache memory including odd numbered index blocks and an even numbered index cache memory including even numbered index blocks. Also, address indexes of requested texture data may be analyzed to appropriately access to at least one of the odd numbered index cache memory and even numbered index cache memory, thereby improving an accessing speed.