Texture Sample Pipeline Lane Mapping for Faster Point Sampling
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Solution Overview
Problem
Graphics processors face inefficiencies in processing point samples due to similar execution rates with bilinear samples, leading to underutilized hardware and increased power consumption.
Innovation Solution
Coalescing point samples into multiple lanes of a sample/filter pipeline, disabling filtering, and power gating unused pipelines to enhance throughput and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If sampling hardware is configured for bilinear sampling with filtering, then filtering quality is improved, but point sample throughput is limited to the same execution rate as bilinear sampling
Solution Approach 1:
The sampling hardware is divided into multiple independent sample pipelines (lanes) within the filtering hardware. Each lane can independently process point samples without requiring full filtering operations, allowing parallel processing of multiple point samples simultaneously. This segmentation enables the hardware to handle point samples at higher throughput while maintaining filtering capability when needed.
2Productivity
If dedicated point sample pipelines are added, then point sample throughput is improved, but device complexity and power consumption increase
Solution Approach 1:
The existing filtering hardware is designed to perform multiple functions: it can execute full bilinear filtering operations when needed, and it can also execute simplified point sample operations by utilizing multiple internal lanes. This multi-functionality eliminates the need for separate dedicated point sample pipelines, reducing hardware complexity while maintaining high point sample throughput.
Solution Approach 2:
Point sample processing capability is merged into the existing filtering hardware structure. By combining point sample operations with the filtering pipeline and utilizing unused computational lanes, the design integrates multiple functions into a single hardware block, avoiding the complexity of separate dedicated pipelines.
3Productivity
If all sample pipelines remain active, then processing capability is maintained, but power consumption increases
Solution Approach 1:
The sampling hardware implements dynamic pipeline selection and activation. Based on the type of sampling operation detected (point sample vs. bilinear sample), the control logic dynamically activates only the necessary number of pipelines. During point sample operations, multiple lanes are activated for high throughput, while during bilinear sampling, the full filtering pipeline is activated. This dynamic adaptation optimizes power consumption by keeping idle pipelines in a low-power state.
Data Source
AI summary
Techniques are disclosed relating to texture sampling, e.g., in graphics processors. In some embodiments, a device includes processor circuitry (e.g., shader pipelines) configured to execute graphics programs and multiple sample pipelines. A given sample pipeline may be configured to, for a multi-texel sample operation specified by the processor circuitry, access texel data for multiple texels forming a first shape in a texture (e.g., a 2×2 square) and perform one or more filter operations to generate a result for the multi-texel sample operation. Point sample control circuitry may be configured to detect that multiple point sample operations, specified by the processor circuitry, access a set of texels having the first shape. The point sample control circuitry may assign the multiple point sample operations to one of the sample pipelines for performance in parallel by the sample pipeline and provide results of the assigned multiple point sample operations to the processor circuitry.