Texture Prefetching Rasterizer Layout for Cache Miss Reduction
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Solution Overview
Problem
Existing graphics processing systems face performance degradation due to cache misses when accessing texture data, particularly with larger textures that span multiple cache lines, leading to substantial delays in texture mapping and rasterization processes.
Innovation Solution
Implement a texture prefetching apparatus with a main and auxiliary rasterizer, each equipped with a tag table, operating in parallel to convert pixel coordinates into cache entries and tags, and manage cache hits and misses to efficiently retrieve texture data from memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If texture data is cached in processor cache memory, then texture mapping performance is improved, but cache memory capacity is limited and texture data often spans numerous cache lines causing cache misses
Solution Approach 1:
The system performs preliminary actions by using the main rasterizer to convert destination coordinates into cache entries and tags before texture mapping is needed. These cache entries and tags are stored in FIFO memories, and the auxiliary rasterizer uses them to proactively fetch texture data from DRAM into cache memory before the main rasterizer needs it, preventing cache misses and stalling.
Solution Approach 2:
The patent introduces intermediary components including two FIFO memories and an auxiliary rasterizer that acts as a mediator between the main rasterizer and texture memory. The auxiliary rasterizer receives cache entries and tags from the main rasterizer, generates memory addresses, and fetches texture data, thereby mediating the data flow and reducing direct memory access delays for the main rasterizer.
2Productivity
If texture data is retrieved from DRAM into cache memory, then texture mapping can proceed, but substantial delays are introduced due to memory access time
Solution Approach 1:
The auxiliary rasterizer performs preliminary action by fetching texture data from DRAM into cache memory before the main rasterizer needs it. By using cache entries and tags generated in advance by the main rasterizer, the auxiliary rasterizer proactively loads texture data, so when the main rasterizer needs the data, it is already available in cache, eliminating memory access delays.
Solution Approach 2:
The system maintains continuity of useful action by having the auxiliary rasterizer continuously fetch texture data based on cache entries and tags from the main rasterizer. This parallel operation ensures that texture data loading continues without interruption, overlapping memory access with rasterization operations to eliminate idle time.
3Area of stationary object
If larger textures are used, then image quality is improved, but texture data spans numerous cache lines leading to unacceptable performance degradation
Solution Approach 1:
For larger textures spanning multiple cache lines, the main rasterizer generates cache entries and tags in advance, and the auxiliary rasterizer uses these to proactively fetch the required texture data into cache memory before it is needed. This preliminary action ensures that even large textures are loaded efficiently, maintaining performance despite the increased data volume.
Solution Approach 2:
The patent segments the texture data access process into two independent rasterizers: the main rasterizer that generates cache entries and tags, and the auxiliary rasterizer that fetches texture data. This segmentation allows parallel processing of texture coordinate conversion and data fetching, improving performance for large textures that require accessing multiple cache lines.
Data Source
AI summary
A texture prefetching apparatus in a graphics processing system having a texture memory is disclosed, comprising a first FIFO memory, a second FIFO memory, a main rasterizer, an auxiliary rasterizer and a cache data memory. The cache data memory is coupled between the first FIFO memory and the texture memory. The main rasterizer converts destination coordinates of a first pixel in a primitive into a cache entry and a tag for a first integer texel according to texture coordinates and destination coordinates of multiple vertices of the primitive. The auxiliary rasterizer coupled to the second FIFO memory converts destination coordinates of N second pixels in the primitive into multiple cache entries, multiple tags and multiple memory addresses for multiple second integer texels according to the texture coordinates and the destination coordinates of the multiple vertices, where N is a multiple of 4.