Textured Dielectric Substrate for Metal Bond Pad Adhesion
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Solution Overview
Problem
The adhesion of metal bond pads to underlying dielectric surfaces in semiconductor devices is inadequate, leading to potential connection failures due to thermal cycling and mechanical stresses, which can result in device failure.
Innovation Solution
A textured substrate with geometric structures formed through photolithography is used to enhance the adhesion of metal bond pads, where the substrate comprises boron phosphate silicate glass (BPSG), and the pattern dimensions and etching processes, such as dry or wet chemical etching, are optimized to create specific geometric profiles that improve bond pad retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a flat dielectric surface is used, then the manufacturing process is simple, but the adhesion of metal bond pads is inadequate
Solution Approach 1:
The patent applies curvature by transforming the flat dielectric surface into a textured surface with geometric structures (circular, rectangular, or triangular patterns). This curvature at micro-scale increases the surface area and mechanical interlocking capability, thereby improving metal bond pad adhesion without requiring fundamental changes to the manufacturing process flow.
Solution Approach 2:
The patent creates a textured dielectric surface with geometric structures that effectively increase surface roughness and surface area. This textured structure provides enhanced mechanical interlocking for metal bond pads, similar to how porous materials increase adhesion through increased surface area and interlocking mechanisms.
2Reliability
If the dielectric surface is textured with geometric structures, then the adhesion of metal bond pads is improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent segments the dielectric surface into distinct geometric structures (circular, rectangular, or triangular patterns) that can be formed using standard photolithography and etching processes. This segmentation approach allows the use of existing manufacturing tools and processes while achieving the desired textured surface for improved adhesion.
Solution Approach 2:
The patent utilizes parameter changes in the photolithography and etching processes to create the textured geometric structures. By adjusting parameters such as photoresist thickness, etch time, and etch chemistry, the desired geometric patterns are formed on the dielectric surface, enabling improved adhesion through standard manufacturing processes.
3Strength
If standard photolithography is used without geometric structures, then the manufacturing process is straightforward, but adhesion fails under thermal stress
Solution Approach 1:
The patent applies preliminary action by forming the geometric structures on the dielectric surface before depositing the metal bond pads. This pre-texturing of the surface ensures that the adhesion-enhancing features are in place before the metal layer is applied, allowing the metal to conform to and bond with the textured surface during the deposition process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The textured substrate significantly increases the adhesion of metal bond pads, reducing the likelihood of connection failures and enhancing the durability of semiconductor devices under stress conditions.
Implementation Method 1
The geometric structure pattern may be formed by through a photolithographic process
Implementation Method 2
the etching processes, such as dry or wet chemical etching, are optimized to create specific geometric profiles
Data Source
AI summary
In various aspects of the disclosure, a semiconductor device including at least one semiconductor die; a dielectric layer adjoining the semiconductor die; geometric structures formed in the dielectric layer; and a conductive layer deposited over the dielectric layer, wherein the conductive layer is at least partially located over the geometric structures.