TFD I/O Partitioning for High-Speed Microelectronic Packages
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Solution Overview
Problem
Conventional microelectronic packages occupy excessive space due to large chip packages and complex interconnections, hindering the integration of numerous chips in compact portable devices and data servers, where size reduction and improved electrical performance are crucial.
Innovation Solution
A microelectronic package design featuring a substrate with apertures and leads connecting microelectronic elements, allowing for efficient signal routing and reduced footprint, with terminals configured to carry address and data signals in a symmetrical and modular fashion, enabling compact and high-performance assemblies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional chip packages are used with large footprints and complex interconnections, then electrical connections and signal routing are established, but the assembly occupies excessive space on the circuit panel
Solution Approach 1:
The invention divides the chip package into a chip carrier and a lead frame, where the lead frame is segmented into multiple sections (first lead section, second lead section, third lead section) that can be independently configured and routed. This segmentation allows for optimized signal paths and reduced interconnection complexity while maintaining electrical functionality.
Solution Approach 2:
The invention transitions from planar interconnections to three-dimensional routing by having leads extend through multiple layers and directions. The lead frame structure utilizes vertical and lateral dimensions to route signals, reducing the horizontal footprint on the circuit panel while maintaining connection integrity.
2Productivity
If more chips are integrated into compact portable devices, then device functionality is enhanced, but the physical space available for interconnections is reduced
Solution Approach 1:
The invention employs a nested structure where the lead frame is embedded within the chip carrier, and leads are routed through multiple levels of the package structure. This nesting allows for high-density interconnections without increasing the external footprint, enabling greater chip integration in compact devices.
Solution Approach 2:
The lead frame structure utilizes three-dimensional routing with leads extending in multiple directions and through multiple layers, transforming the interconnection problem from a two-dimensional plane to a three-dimensional space, thereby increasing integration density.
3Reliability
If symmetrical terminal configurations are used for address and data signals, then electrical performance and signal routing efficiency are improved, but the design flexibility is constrained
Solution Approach 1:
The invention employs asymmetrical lead frame configurations where different lead sections are assigned to different signal types (address signals vs. data signals) based on their specific routing requirements. This asymmetry allows optimized electrical performance for each signal type while maintaining overall design flexibility through the modular lead frame structure.
Data Source
AI summary
A microelectronic package can include a substrate having first and second surfaces, first, second, and third microelectronic elements each having a surface facing the first surface, terminals exposed at the second surface, and leads electrically connected between contacts of each microelectronic element and the terminals. The substrate can have first, second, and third spaced-apart apertures having first, second, and third parallel axes extending in directions of the lengths of the apertures. The contacts of the first, second, and third microelectronic elements can be aligned with one of the first, second, or third apertures. The terminals can include first and second sets of first terminals configured to carry address information. The first set can be connected with the first and third microelectronic elements and not with the second microelectronic element, and the second set can be connected with the second microelectronic element and not with the first or third microelectronic elements.