TFET 3D NAND Cell Structure for Threshold Voltage Stability
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Solution Overview
Problem
Frequent applications of bias voltage in 3D NAND memory devices disturb charge trapping in charge-trapping layers, leading to undesirable shifts in threshold voltages and reliability issues during operations like reading, programming, and erasing.
Innovation Solution
Incorporating tunnel field effect transistors (TFET) with a semiconductor channel surrounded by dielectric layers, including a tunneling, charge-trapping, and blocking layer, reduces the frequency of voltage bias applications, thereby minimizing disturbance to trapped charges and enhancing threshold voltage stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bias voltage is frequently applied to operate memory cells, then memory device functionality is maintained, but charge trapping in charge-trapping layer is disturbed causing threshold voltage shifts
Solution Approach 1:
The patent changes the operating parameters of the memory device by reducing the frequency of bias voltage application. This allows charge trapping in the charge-trapping layer to remain stable while still maintaining necessary memory cell functionality through less frequent read, program, and erase operations.
Solution Approach 2:
The patent implements periodic action by applying bias voltage only when necessary for memory operations rather than continuously. This periodic activation reduces disturbance to the charge-trapping layer while maintaining memory device functionality through scheduled operation cycles.
2Quantity of substance
If 3D NAND memory structure is used to increase bit density, then storage capacity is improved, but charge trapping disturbance during operations increases
Solution Approach 1:
The patent changes operational parameters to reduce the frequency and intensity of bias voltage application in 3D NAND memory structures. This approach maintains the high bit density advantage while reducing the disturbance to charge trapping that occurs during frequent memory operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of TFET in 3D NAND memory cells improves threshold voltage stability and reliability by reducing read, pass, and program disturbance errors, leading to more reliable device operations.
Implementation Method 1
tunneling layer
Implementation Method 2
charge-trapping layer where the charge-trapping layer can trap or de-trap charges
Data Source
AI summary
Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a plurality vertical memory strings disposed through an alternating conductor/dielectric stack. Each of the memory strings includes a composite dielectric layers and a TFET semiconductor layer. The TFET semiconductor layer includes an n-type semiconductor layer and a p-type semiconductor layer.