Tunnel Transistors with Abrupt Junctions via Self-Aligned Etch
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Solution Overview
Problem
Conventional junction tunnel transistors (TFETs) face challenges in achieving controlled gate overlap and minimizing gate dielectric damage due to isotropic etching, leading to high gate leakage and parasitic capacitance, which affects sub-threshold swing and overall performance.
Innovation Solution
A self-aligned etch cavity process is employed to grow a thin epitaxial channel region over the source, using a high-k gate dielectric and metal gate stack, with anisotropic and sigma-shaped etches to form a replacement gate structure that reduces gate-source overlap and enhances BTBT current directionality, thereby improving sub-threshold swing and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If isotropic etch is used to undercut the gate electrode for Ge source placement, then sub-60 mV/dec SS is achieved, but gate dielectric is damaged and gate leakage increases
Solution Approach 1:
The patent introduces a mandrel structure as an intermediary element during the etching process. The mandrel protects the gate dielectric from direct exposure to isotropic etch, allowing the Ge source to be placed under the gate dielectric without damaging the dielectric layer. This mediator enables the beneficial undercut effect while preventing the harmful dielectric damage.
2Reliability
If Ge source is placed directly under gate dielectric for optimal BTBT current, then sub-60 mV/dec SS is achieved, but gate leakage increases due to dielectric exposure to isotropic etch
Solution Approach 1:
The mandrel acts as a protective intermediary that enables direct Ge source placement under the gate dielectric while preventing etch-induced dielectric damage. This allows optimal BTBT current flow without the harmful side effect of gate leakage from dielectric exposure.
3Device complexity
If vertical TFET design is used for compact structure, then device integration is improved, but parasitic capacitance increases due to gate-source overlap
Solution Approach 1:
The patent transitions from a planar gate-source overlap configuration to a three-dimensional configuration where the Ge source is positioned underneath the gate dielectric in the vertical dimension. This dimensional change reduces the overlapping area between gate and source, thereby reducing parasitic capacitance while maintaining the compact vertical TFET structure.
4Ease of manufacture
If isotropic etch is used to achieve gate undercut, then Ge source placement under gate is enabled, but manufacturing precision is reduced due to difficulty in controlling etch extent
Solution Approach 1:
The mandrel serves as a precision-controlling intermediary that defines the exact extent of the isotropic etch undercut. By controlling the mandrel dimensions and position, the gate overlap and Ge source placement can be precisely controlled, eliminating the manufacturing precision issues associated with uncontrolled isotropic etching.
Solution Approach 2:
The mandrel is placed in advance before the isotropic etch process, pre-defining the protection boundaries and etch extent. This preliminary action enables precise control of the gate undercut and Ge source placement, transforming an otherwise difficult-to-control process into a precision-manageable fabrication step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for precise control of gate overlap, reduces gate leakage, and enhances the sub-threshold swing and drive current of TFETs, leading to improved performance and reduced off-state leakage.
Implementation Method 1
a thin epitaxial channel region that is grown within the self-aligned etch cavity, covering at least the first or the second source region
Implementation Method 2
in TFETs a tunnel energy barrier is modulated at the source region, as opposed to a thermal barrier at the source region. It is the modulation of this tunnel barrier (in particular, a band-to-band tunnel (BTBT) barrier) which results in a drain-current-to-gate-voltage sensitivity
Data Source
AI summary
A tunnel field effect transistor (TFET) including a first doped source region for a first type TFET or a second doped source region for a second type TFET; a second doped drain region for the first type TFET or a first doped drain region for the second type TFET; a body region that is either intrinsic or doped, with a doping concentration less than that of the first or second source region, separating the first or second source from the first or second drain regions; a self-aligned etch cavity separating the first or second doped source and drain regions; a thin epitaxial channel region that is grown within the self-aligned etch cavity, covering at least the first or the second source region; a replacement gate stack comprising a high-k gate dielectric and one or a combination of metals and polysilicon; and sidewall spacers adjacent to the replacement gate stack.