Tunnel FET Gate Offset for Sub-60mV/Decade Slope
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Solution Overview
Problem
Downscaling of CMOS technology is hindered by the non-scalability of the sub-threshold slope in traditional MOSFET devices, and while TFETs offer a temperature-independent low sub-threshold swing, they face limitations due to low tunneling rates and complex, costly manufacturing processes.
Innovation Solution
A tunnel FET device with a steep sub-threshold slope is achieved by arranging a conductive gate electrode laterally offset from the conductive drain electrode, controlling tunneling of majority carriers and diffusion of minority carriers to modulate the effective barrier height, thereby enabling a sub-threshold slope of below 60 mV/decade through two exponential control mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional MOSFET devices are used, then manufacturing is simple and well-established, but sub-threshold slope cannot be reduced below thermal limit of 60 mV/decade
Solution Approach 1:
The device is segmented into distinct functional regions: a drift region with specific doping concentration, a depletion region formed by the gate electrode, and a tunneling region. This segmentation allows independent optimization of each region to achieve sub-60mV/decade sub-threshold slope while maintaining manufacturability through standardized semiconductor processing techniques.
Solution Approach 2:
The invention changes key physical parameters including doping concentration in the drift region (10^16 to 10^18 atoms/cm³), depletion region width (10nm to 100nm), and gate electrode configuration to achieve steep sub-threshold slope. These parameter changes enable the device to operate below the thermal limit while using conventional manufacturing processes.
2Manufacturing precision
If TFETs are used to achieve temperature-independent low sub-threshold swing, then sub-threshold slope can be reduced below 60 mV/decade, but tunneling rates are low and manufacturing processes are complex and costly
Solution Approach 1:
The invention applies local quality by creating a depletion region with specific electrical characteristics localized between the gate electrode and drain electrode. This localized depletion region with controlled width and doping enables high tunneling rates in the critical switching region while maintaining overall device performance and compatibility with standard manufacturing.
Solution Approach 2:
The invention replaces the traditional tunneling mechanism with a field-effect controlled depletion region mechanism. Instead of relying solely on quantum tunneling through a barrier, the gate electrode electrically controls a depletion region that modulates carrier flow, achieving steep sub-threshold slope through electrical field control rather than purely mechanical tunneling barrier design.
3Manufacturing precision
If gate electrode is positioned to control tunneling effectively, then sub-threshold slope improves, but device structure becomes more complex
Solution Approach 1:
The gate electrode serves multiple functions simultaneously: it creates the depletion region, controls the tunneling barrier height, modulates carrier flow, and defines the active channel region. This multi-functionality achieves steep sub-threshold slope without requiring additional specialized electrodes or complex structures, maintaining device simplicity while improving performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for high switching speeds and scalable supply voltage with a reduced sub-threshold slope, overcoming the thermal limitations of traditional MOSFETs and improving drive current without the complexity and cost of traditional manufacturing processes.
Implementation Method 1
controlling tunneling of majority carriers within the dielectric layer
Implementation Method 2
controlling the diffusion of minority carrier within the substrate
Data Source
AI summary
The present disclosure relates to a tunnel FET device with a steep sub-threshold slope, and a corresponding method of formation. In some embodiments, the tunnel FET device has a dielectric layer arranged over a substrate. A conductive gate electrode and a conductive drain electrode are arranged over the dielectric layer. A conductive source electrode contacts the substrate at a first position located along a first side of the conductive gate electrode. The conductive drain electrode is arranged at a second position located along the first side of the conductive gate electrode. By arranging the conductive gate electrode over the dielectric layer at a position laterally offset from the conductive drain electrode, the conductive gate electrode is able to generate an electric field that controls tunneling of minority carriers, which can change the effective barrier height of the tunnel barrier, and thereby improving a sub-threshold slope of the tunnel FET device.