Tunnel Field Effect Transistor Using III-V Heterojunctions
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Solution Overview
Problem
Existing Tunnel Field Effect Transistors (TFETs) require high doping concentrations in source and drain regions, leading to potential amorphosization and limitations in scaling due to high energy implantation, which affects tunneling current density and device performance.
Innovation Solution
The use of III-V based materials with type-II band offsets, Fermi level pinning, and in-situ doping to fabricate TFETs, eliminating the need for high energy implantation and reducing doping concentrations, while introducing a delta layer to lower valence band offsets and increase tunneling probability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high doping concentrations are used in source and drain regions, then tunneling current density is improved, but amorphosization occurs and scaling is limited
Solution Approach 1:
The patent changes the material parameter from silicon-based to III-V compound semiconductors (GaAs, InAs, InP) which have different band structures and higher carrier mobility. This material substitution enables achieving high tunneling current density without requiring extreme doping concentrations that would cause amorphosization, thus resolving the contradiction between reliability and manufacturing precision
Solution Approach 2:
The patent employs composite material structures including heterojunctions (e.g., InAs/GaAs, InP/GaAs) and type-II band alignment configurations. These composite structures create favorable band offsets that enhance tunneling probability while maintaining crystalline integrity, allowing high current density without the harmful effects of high doping
2Quantity of substance
If high energy implantation is used to achieve high doping, then doping concentration is improved, but device performance is limited due to damage
Solution Approach 1:
The patent extracts the high energy implantation step from the fabrication process by utilizing in-situ doped epitaxial growth. This eliminates the damaging effects of ion implantation while maintaining the ability to achieve required doping concentrations through controlled material deposition, thus preserving device performance
Solution Approach 2:
The patent replaces the mechanical/physical process of ion implantation with a chemical vapor deposition or molecular beam epitaxy process. This substitution allows for precise doping control during epitaxial growth without the mechanical damage caused by high energy ion bombardment, maintaining both doping concentration and device performance
3Productivity
If conventional CMOS scaling is continued, then transistor density is improved, but off-state leakage current increases
Solution Approach 1:
The patent changes the fundamental operating parameter of the transistor by using III-V materials with direct band gaps and type-II band alignments. These material parameters enable exponential suppression of off-state leakage current through enhanced band-to-band tunneling control, allowing continued scaling without the leakage penalties that plague conventional CMOS
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances tunneling current density and reduces the need for high doping, improving TFET performance by increasing tunneling probability and reducing the risk of amorphosization, thereby enabling better scaling and lower off-state leakage current.
Implementation Method 1
The source and channel regions form a hetero junction having type-II band offsets that enable band-to-band tunneling
Implementation Method 2
the introduction of what is referred to as a delta layer between source and channel regions lowers the valence band offset and band gap at the tunneling junction
Data Source
Figure 1~2
Figure 3
Figure 4
AI summary
A TFET includes a source region (110, 210), a drain region (120, 220), a channel region (130, 230) between the source region and the drain region, and a gate region (140, 240) adjacent to the channel region. The source region contains a first compound semiconductor including a first Group III material and a first Group V material, and the channel region contains a second compound semiconductor including a second Group III material and a second Group V material. The drain region may contain a third compound semiconductor including a third Group III material and a third Group V material.