TFET Interlayer Reduces Trap-Assisted Tunneling Leakage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional MOSFETs are limited by a sub-threshold swing of 60 mV/decade due to the drift-diffusion transport mechanism, making it challenging to achieve faster switching at low operation voltages, while TFETs, which rely on quantum tunneling, can potentially overcome this limitation but require innovative designs to enhance their performance.
Innovation Solution
Incorporating a wide bandgap semiconductor interlayer between the channel and the gate dielectric in TFETs to increase the physical and energetic distance for trap-assisted tunneling, thereby suppressing this effect and maintaining the main band-to-band tunneling pathway, which reduces the sub-threshold swing and OFF-state current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an interlayer is added between the channel and gate dielectric, then trap-assisted tunneling leakage is reduced, but device structure becomes more complex
Solution Approach 1:
An interlayer comprising a semiconductor material with a wider bandgap than the channel material is inserted between the channel and gate dielectric. This interlayer acts as an intermediary that increases the physical distance and energy barrier for trap-assisted tunneling pathways, thereby reducing OFF-state leakage current while maintaining band-to-band tunneling functionality.
Solution Approach 2:
The device employs composite material structure where the interlayer semiconductor material (e.g., GaN, AlN, or InGaN) is combined with the channel material (e.g., InN or InGaN). This composite structure leverages the wider bandgap properties of the interlayer material to suppress trap-assisted tunneling while preserving the desired electrical characteristics of the channel.
2Reliability
If the physical distance for trap-assisted tunneling is increased, then TAT leakage is suppressed, but the main tunneling pathway may be affected
Solution Approach 1:
The interlayer is strategically positioned only between the channel and gate dielectric, creating a localized modification that specifically targets trap-assisted tunneling pathways near the gate interface. The band-to-band tunneling pathway through the channel remains unaffected because the interlayer does not interfere with the source-to-drain tunneling mechanism.
Solution Approach 2:
The semiconductor material of the interlayer is selected to have a wider bandgap than the channel material, changing the energy barrier parameter for trap-assisted tunneling. This parameter change increases the energy required for TAT while maintaining appropriate parameters for band-to-band tunneling in the channel.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively decreases the sub-threshold swing and reduces the OFF-state current, enabling improved switching speed and efficiency in TFETs without affecting the band-to-band tunneling, thus enhancing the performance of nanoscale devices.
Implementation Method 1
increases the physical distance for charge carriers to reach the interface of the semiconductor/dielectric junction from the channel layer under the trap-assisted tunneling (TAT) effect and also increases the energy barrier for TAT tunneling
Implementation Method 2
the major band to band tunneling (BTBT) effect from the source to the drain through the channel is not affected by the additional interlayer because the interlayer is not in the route of the BTBT
Data Source
AI summary
The current disclosure describes a tunnel FET device including a P-I-N heterojunction structure. A high-K dielectric layer and a metal gate wrap around the intrinsic channel layer with an interlayer positioned between high-K dielectric layer and the intrinsic channel layer of the P-I-N heterojunction. The interlayer prevents charge carriers from reaching the interface with high-K dielectric layer under the trap-assisted tunneling effect and reduces OFF state leakage.