TFET Source Metal Pocket Layer Schottky Junction

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In tunnel field-effect transistors (TFETs), increasing the tunneling current is challenging due to limitations in carrier tunneling efficiency, which can only be improved by increasing the pocket layer area, leading to reduced chip integration density.

Innovation Solution

A TFET structure is developed with a metal layer in the source region and a Schottky tunnel junction formed by the pocket layer and metal layer, allowing for higher tunneling efficiency without increasing the pocket layer area, thereby maintaining a compact layout and improving integration density.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the area of the pocket layer is increased to increase tunneling current, then the tunneling current increases, but the layout area of the TFET increases and integration density decreases

Engineering Contradiction:
Improvetunneling currentVSAvoidlayout area
Core Design Contradiction:
Quantity of substanceVSArea of stationary object

Solution Approach 1:

The patent introduces a metal layer with different material properties (higher carrier concentration) into a specific region of the source region. This creates local quality variation where the metal layer area provides enhanced tunneling current while the rest of the structure maintains compact dimensions, thus increasing tunneling current without proportionally increasing the overall layout area

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent combines metal material (such as tungsten, molybdenum, or titanium nitride) with semiconductor material in the source region to form a composite structure. The metal layer provides high carrier concentration for efficient tunneling, while the semiconductor material maintains the device structure, achieving high tunneling current with compact layout area

Inventive Principle:
Principle #40Composite materials

2Quantity of substance

If the carrier tunneling efficiency is increased to increase tunneling current, then the tunneling current increases, but technical limitations make it difficult to improve carrier tunneling efficiency

Engineering Contradiction:
Improvetunneling currentVSAvoidtechnical limitation
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent changes the material parameter (carrier concentration) by introducing a metal layer with inherently higher carrier concentration than the semiconductor material. This parameter change directly enhances the tunneling efficiency without requiring complex structural modifications or process changes, overcoming the technical limitations mentioned

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The TFET achieves increased tunneling current with improved carrier tunneling efficiency through the Schottky tunnel junction, enhancing chip integration density without expanding the layout area.

Implementation Method 1

the pocket layer and the metal layer form a Schottky tunnel junction of the tunnel field-effect transistor, and the second area and the metal layer form a first tunnel junction of the tunnel field-effect transistor

Methodology Applied
Scientific EffectTunneling effect: Franz-Keldysh Effect

Data Source

PatentUS10446672B2Tunnel field-effect transistor and tunnel field-effect transistor production method
Publication Date: 2019.10.15 HUAWEI TECH CO LTD
  • US10446672B2 patent drawing
  • US10446672B2 patent drawing
  • US10446672B2 patent drawing

AI summary

A tunnel field-effect transistor (TFET) is provided. In the TFET, a channel region (202) connects a source region (201) and a drain region (203); a pocket layer (204) and a gate oxide layer (205) are successively produced between the source region and a gate region (206); a metal layer (208) is produced in a first area in the source region, the first area is located on a side on which the source region is in contact with the pocket layer, and the pocket layer covers at least a part of the metal layer; and the pocket layer and a second area in the source region form a first tunnel junction of the TFET, and the pocket layer and the metal layer form a second tunnel junction of the TFET.