TFET Nanowire Source Gate-All-Around Drain Pad
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Solution Overview
Problem
Tunnel field effect transistors (TFETs) face inefficiencies due to parasitic ambipolar behavior caused by high fields at the drain end of nanowire channel TFETs, leading to increased off current.
Innovation Solution
A TFET design featuring a nanowire source region, channel region, and a drain region on a silicon pad, with a gate configuration that surrounds the channel and source region, suppressing ambipolar behavior by using a gate-all-around (GAA) geometry and forming the drain in a planar single-gated region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a nanowire channel TFET is used to achieve good electrostatic control, then electrostatic control is improved, but parasitic ambipolar behavior increases leading to higher off current
Solution Approach 1:
The device is segmented into distinct source, channel, and drain regions with different gate configurations. The source and channel regions have gate-all-around (GAA) geometry for strong electrostatic control, while the drain region transitions to planar single-gated geometry to suppress ambipolar behavior. This segmentation allows each region to be optimized for its specific function.
Solution Approach 2:
Different gate geometries are applied to different regions of the device. The source and channel regions utilize gate-all-around (GAA) configuration for maximum electrostatic control, while the drain region uses planar single-gated configuration to eliminate parasitic ambipolar effects. This local differentiation of gate structure quality resolves the contradiction between electrostatic control and ambipolar suppression.
2Reliability
If gate-all-around (GAA) geometry is used to control the channel, then electrostatic control is improved, but ambipolar behavior increases
Solution Approach 1:
The gate structure is segmented such that GAA geometry is applied only to the source and channel regions where strong electrostatic control is needed, while the drain region transitions to planar single-gated geometry. This segmentation prevents ambipolar behavior from occurring in the drain region while maintaining excellent electrostatic control in the source and channel.
Solution Approach 2:
The gate geometry is locally optimized: gate-all-around (GAA) configuration is used in the source and channel regions to maximize electrostatic control, while planar single-gated configuration is used in the drain region to suppress ambipolar behavior. This local differentiation resolves the contradiction by applying the appropriate gate geometry quality to each specific region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the off current in TFETs by effectively controlling electrostatics and minimizing ambipolar behavior, resulting in a more efficient device.
Implementation Method 1
A TFET may comprise a nanowire channel, which may provide good electrostatic control of the channel due to gate-all-around (GAA) geometry
Implementation Method 2
Tunnel field effect transistors (TFETs) may be used as a replacement for or complement to metal-oxide-semiconductor FETs (MOSFETs)
Data Source
AI summary
A tunnel field effect transistor (TFET) includes a source region, the source region comprising a first portion of a nanowire; a channel region, the channel region comprising a second portion of the nanowire; a drain region, the drain region comprising a portion of a silicon pad, the silicon pad being located adjacent to the channel region; and a gate configured such that the gate surrounds the channel region and at least a portion of the source region.