TFET and Planar Device Integration on Single Substrate
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Solution Overview
Problem
The integration of tunnel field-effect transistors (TFETs) and conventional planar structures in semiconductor devices is complex and costly due to the limitations of TFET structure characteristics, leading to increased process complexity and power consumption.
Innovation Solution
A semiconductor device and method where a TFET and a planar device are integrated on the same substrate, with the TFET and planar device sharing a common surface, reducing the need for separate baseplates and simplifying the fabrication process by forming layers of the same material in a single process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a TFET and conventional planar structure are integrated using separate baseplates, then the device functionality is achieved, but the process complexity and implementation costs increase significantly
Solution Approach 1:
The patent merges the TFET and planar structure onto a single substrate, eliminating the need for separate baseplates and reducing integration complexity. The TFET is formed with source and drain regions, and the planar structure is integrated on the same substrate, achieving both functionalities in a unified device architecture.
Solution Approach 2:
The single substrate serves multiple functions by simultaneously supporting both the TFET and the planar structure. This multi-functional approach allows the substrate to accommodate different device types without requiring separate integration processes, thereby reducing overall device complexity.
2Adaptability or versatility
If a TFET and conventional planar structure are integrated using separate baseplates, then the device functionality is achieved, but the implementation costs increase
Solution Approach 1:
The patent combines the TFET and planar structure on a single substrate, which reduces the number of fabrication steps and materials required. This merging approach lowers implementation costs by eliminating the need for separate baseplate preparation, alignment, and bonding processes.
3Reliability
If the TFET structure is formed first and then the planar structure is added, then the TFET characteristics are preserved, but the process complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming the TFET structure first with properly doped source and drain regions, then subsequently integrating the planar structure. This sequential approach ensures that the TFET characteristics are established before adding additional functionality, maintaining reliability while managing process complexity.
4Productivity
If CMOS size is reduced to achieve higher integration density, then the performance and integration density improve, but the power consumption increases
Solution Approach 1:
The patent employs parameter changes by utilizing a tunnel field-effect transistor with a steep subthreshold slope, which allows for lower operating voltages. This parameter optimization enables reduced power consumption even at smaller device sizes, counteracting the typical increase in leakage current associated with scaling.
Data Source
AI summary
A semiconductor device and a method for fabricating a semiconductor device are disclosed. The semiconductor device includes a tunnel field-effect transistor and a planar device. The tunnel field-effect transistor includes a first substrate and a first electrical element, and the first electrical element is formed on one side of the first substrate; the planar device includes a second substrate and a second electrical element, the second substrate and the first substrate are an integrated structure and form a main substrate, the second electrical element is formed on one side of the second substrate, and the second electrical element and the first electrical element are disposed on a same side of the main substrate; and the planar device includes any one of a metal oxide semiconductor transistor, a capacitor, and a resistor.