Tunnel Field-Effect Transistor With Protruding Source Interface
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Solution Overview
Problem
Tunnel field-effect transistors (TFETs) face challenges in reducing the slope of subthreshold voltage and increasing on-currents due to the limitations of current semiconductor device scaling, which affects power consumption and performance.
Innovation Solution
A semiconductor structure and method for fabricating TFETs involving a gate structure with doped source/drain layers of opposite conductivity types, where the contact interface between the source/drain layers and the channel region has protruding structures to enhance the electric field, thereby increasing the on-current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the critical dimension of semiconductor devices is continuously reduced to increase transistor density, then more transistors can be formed in a single chip, but the short-channel effect increases and leakage current increases
Solution Approach 1:
The source and drain regions are segmented into multiple doped layers with different conductivity types (first doped source/drain layer and second doped source/drain layer with opposite conductivity). This segmentation creates a more complex internal structure that helps control the short-channel effect while maintaining high transistor density.
Solution Approach 2:
Different regions of the source/drain structure are doped with different types of ions to create local variations in conductivity. The first doped source/drain layer and second doped source/drain layer have opposite conductivity types, creating localized electrical properties that optimize both density and reliability.
2Productivity
If the size of transistors is rapidly reduced to increase integration, then chip capacity increases, but the subthreshold voltage slope is limited to 60 mV/dec at room temperature
Solution Approach 1:
The invention changes the electrical parameters of the source/drain regions by introducing multiple doped layers with opposite conductivity types. This parameter change enables better control over the subthreshold voltage slope, allowing it to overcome the conventional 60 mV/dec limitation at room temperature while maintaining high transistor integration.
3Reliability
If conventional TFET structures are used, then the basic tunneling mechanism is maintained, but the on-current is insufficient and the subthreshold voltage slope cannot be further reduced
Solution Approach 1:
The source/drain structure uses a composite of multiple doped layers with opposite conductivity types. This composite structure enhances the tunneling effect by creating favorable band alignment and electric field distribution, thereby increasing the on-current while maintaining the stability of the quantum tunneling mechanism.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The enhanced electric field allows for increased electron tunneling, reducing the slope of subthreshold voltage and enhancing the on-current of TFETs, improving their performance and power efficiency.
Implementation Method 1
TFETs utilize the quantum tunneling effect as the major mechanism to control the current; and a gate voltage to control the shape of the potential distribution inside the devices so as to affect the conditions to have the quantum tunneling effect.
Implementation Method 2
a first contact interface between the first doped source/drain layer and the channel region has protruding structures protruding toward a channel region under the gate structure
Data Source
AI summary
Tunnel field-effect transistors are provided. A tunnel field-effect transistor (TFET) includes a semiconductor substrate; a gate structure having a first side and an opposing second side formed on the semiconductor substrate. A first doped source/drain layer is formed in the semiconductor substrate at the first side of the gate structure. The first doped source/drain layer is doped with a first type of doping ions and a first contact interface between the first doped source/drain layer and a channel region of the semiconductor substrate has a plurality of protruding structures protruding toward the channel region under the gate structure. A second doped source/drain layer in the semiconductor substrate at the second side of the gate structure. The second doped source/drain layer is doped with a second type of doping ions having a conductive type opposite to the first source/drain doping layer.