Self-Aligned Planar TFET Fabrication via Hard Mask Alignment
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Solution Overview
Problem
The fabrication of tunneling field-effect transistors (TFETs) using conventional planar processes is hindered by alignment deviations in photolithography, leading to unstable device characteristics and high parasitic capacitance due to the need for precise alignment of differently doped source and drain regions, which restricts further downscaling of device dimensions and integration with traditional CMOS technology.
Innovation Solution
A self-aligned planar process for fabricating TFETs is developed, utilizing shallow trench isolation, gate dielectric growth, and chemical mechanical polishing to define channel, source, and drain regions with different hard dielectric materials, reducing the reliance on precise photolithography and minimizing overlap between gate and source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography process is used to define source and drain regions, then device fabrication can proceed, but alignment deviation occurs leading to unstable device characteristics
Solution Approach 1:
The gate region is formed first as a self-aligned mask before defining the source and drain regions. This preliminary formation of the gate structure enables subsequent self-aligned ion implantation processes, eliminating the need for separate photolithography alignment steps and thereby resolving the alignment precision issue
Solution Approach 2:
The gate structure and previously formed regions serve as self-aligned masks for subsequent doping processes. The ion implantation is performed through openings in the isolation layer that are automatically aligned to the gate and other regions, allowing the structure itself to define the precise locations of source and drain regions without external alignment intervention
2Device complexity
If overlap between gate region and source/drain regions is increased to simplify fabrication, then manufacturing complexity is reduced, but parasitic capacitance increases
Solution Approach 1:
The gate region is formed first with precise dimensions before the source and drain regions are defined. This preliminary formation establishes the gate as a reference structure, allowing minimal overlap to be achieved while maintaining fabrication simplicity through self-aligned processes
Solution Approach 2:
The patent replaces photolithography-based mechanical alignment with field-based self-alignment using ion implantation through selectively opened isolation layers. This substitution allows precise control of overlap dimensions without increasing photolithography complexity, thereby reducing parasitic capacitance while maintaining manufacturing simplicity
3Productivity
If device dimension is scaled down to improve performance and reduce cost, then integration density increases, but short channel effects become more severe
Solution Approach 1:
The self-aligned fabrication process ensures precise positioning of source and drain regions relative to the gate, minimizing overlap and reducing parasitic capacitance. This precision enables better control of short channel effects at scaled dimensions while maintaining high integration density
Solution Approach 2:
The gate structure is formed first as a self-aligned reference, enabling precise definition of source and drain regions at minimal overlap distances. This preliminary gate formation allows accurate control of critical dimensions even at scaled device sizes, improving short channel effect control while enabling higher integration density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for stable and reliable fabrication of TFETs with reduced parasitic capacitance and improved integration compatibility with traditional CMOS technology, alleviating alignment deviation issues and enabling further downscaling of device dimensions for low power consumption applications.
Implementation Method 1
forming a gate dielectric layer on the silicon substrate
Implementation Method 2
depositing polysilicon on the gate dielectric layer
Implementation Method 3
chemical mechanical polishing to define channel, source, and drain regions
Data Source
AI summary
The present invention discloses a method for self-alignedly fabricating tunneling field-effect transistor (TFET) based on planar process, thereby lowering requirements on a photolithography process for fabricating the planar TFET. In the method, the source region and the drain region of the TFET are not directly defined by photolithography; rather, they are defined by another dielectric film which locates over an active region and on both sides of the gate and which is different from the dielectric film that defines the channel region. The influence due to the alignment deviation among three times of photolithography process for defining the channel region, the source and the drain regions may be eliminated by selectively removing the dielectric film over the source and drain regions by wet etching. Therefore, a planar TFET may be fabricated self-alignedly based on this process, thereby the rigid requirements on the alignment deviation of the photolithography during the fabrication procedure of a planar TFET is alleviated, which facilitates to fabricate a planar TFET device with stable and reliable characteristics.