Line-Tunneling TFET Source Segmentation for Low Power
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Solution Overview
Problem
Tunnel field effect transistors (TFETs) face challenges with increasing power consumption due to leakage currents and limited subthreshold swing, which hinders the reduction of supply voltage, and all-silicon TFETs suffer from low on-currents due to high tunnel barrier resistance.
Innovation Solution
A TFET design with a source-channel-drain structure featuring a gate electrode that covers only the source region, incorporating a second source sub-region with a higher doping concentration as a pocket region to enhance tunneling efficiency, reducing the impact of drain-source voltage variations and achieving subthreshold swing less than 60 mV/decade.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the gate electrode covers only the source region (line tunneling configuration), then the subthreshold swing is reduced below 60 mV/decade and power consumption is lowered, but the device complexity increases due to the need for precise gate positioning and dual doping profiles
Solution Approach 1:
The source region is segmented into two distinct sub-regions: a first source sub-region with a first doping profile and a second source sub-region with a second doping profile having a higher peak concentration. This segmentation allows independent optimization of each region's doping characteristics to achieve line tunneling with sub-60mV/decade subthreshold swing while managing the complexity through structured regional division
Solution Approach 2:
Different doping profiles are applied to different parts of the source region. The first source sub-region receives a first doping profile while the second source sub-region receives a second doping profile with higher peak concentration. This local quality variation enables precise control of the tunneling characteristics in the line tunneling configuration, achieving low power consumption without uniform complexity throughout the device
2Reliability
If a second source sub-region with higher doping concentration is added to create a pocket region, then tunneling efficiency is enhanced and onset voltage spread is reduced, but the manufacturing precision requirements increase
Solution Approach 1:
The second source sub-region with higher doping concentration is formed as a pocket region in advance, before the final device operation. This preliminary action of creating the high-doping pocket region ensures that the tunneling efficiency is optimized from the outset, reducing the spread of onset voltage and enhancing reliability without requiring precision adjustments during operation
Solution Approach 2:
The doping concentration parameter is changed by creating a second source sub-region with a second doping profile that has a higher peak concentration than the first doping profile. This parameter change in the doping concentration enables enhanced tunneling efficiency and reduced onset voltage spread, with the manufacturing precision challenge addressed through controlled doping process parameters
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design significantly reduces the spread of onset voltage with variations in source-drain voltage, improving TFET performance by controlling tunneling currents and maintaining low power consumption.
Implementation Method 1
the tunneling effect is based on band-to-band tunneling
Implementation Method 2
Because of the higher doping concentration in the second doping profile, a higher tunneling efficiency is obtained
Data Source
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AI summary
A tunnel field effect transistor (TFET) (100) is disclosed comprising a source-channel-drain structure comprising at least one doped source region (30), at least one doped drain region (22) and at least one channel region (21) situated between the source region (30) and the drain region (22) and forming a source-channel interface (201) with the source region (30) and a drain-channel interface (202) with the drain region (22). The source region (30) comprises a first source sub-region (20) which is doped with a first doping profile (1011) with a dopant element of a first doping type having a first peak concentration (1021) and further comprises a second source sub-region (25) close to the source-channel interface (201) which is doped with a second doping profile (1012) with a second dopant element with the same doping type as the first dopant element and having a second peak concentration (1022) and wherein an interface (1014) is defined between the first doping profile (1011) and the second doping profile (1012). The second peak concentration (1022) of the second doping profile (1012) is substantially higher than the maximum doping level (1023) of the first doping profile (1011) close to the interface (1014) between the first and the second source sub-regions (20, 25). The TFET (100) further comprises a gate electrode (24) which covers at least part of the source region (30) along the longitudinal direction (L) thereof such that there is no coverage by the gate electrode (24) of the channel region (21) nor of the drain region (22) and a gate dielectric (29) along the longitudinal direction (L) in between the gate electrode (24) and the source region (30).