TFET Fabrication Using Spacer-Layer Etch Stop for Precise Heterojunction Alignment
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Solution Overview
Problem
Current field-effect transistors, particularly MOSFETs, are limited by a subthreshold swing of 60 mV/dec, which restricts power scaling and speed, while TFETs face challenges in achieving high performance due to process complexity and sensitivity to defects, especially in achieving a CMOS-compatible process flow.
Innovation Solution
A method for fabricating field-effect transistors involving precise control of etching to form an undercut below a spacer layer, allowing for precise positioning of semiconductor structures relative to the gate, enabling a self-aligned gate and heterojunction placement with nanometer precision, and potentially reducing subthreshold swing below 60 mV/dec by using a semiconductor layer with a lower etch rate than the first semiconductor structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a self-aligned gate fabrication process is used to achieve precise positioning of semiconductor structures, then manufacturing precision is improved, but the process complexity increases due to the need for precise etching control and alignment
Solution Approach 1:
The spacer layer serves a dual function: it acts as both a structural component defining the gate alignment and as an etch-stop layer that automatically prevents over-etching. This self-regulating mechanism eliminates the need for complex external control systems, achieving precise positioning through the material's inherent properties rather than complex process control
Solution Approach 2:
The invention exploits the difference in etch rates between the first semiconductor structure and the spacer layer as a controllable parameter. By selecting materials with distinct etch rate characteristics, the process achieves precise positioning through material property differentiation rather than complex geometric control, simplifying the fabrication process
2Manufacturing precision
If the etchant is allowed to deeply recess the first semiconductor structure to achieve precise alignment, then manufacturing precision is improved, but the risk of damaging the gate structure increases
Solution Approach 1:
The spacer layer is deposited beforehand as a protective cushion between the etchant and the gate structure. This pre-positioned protective layer absorbs the etching action and prevents the etchant from reaching and damaging the gate structure, while still allowing precise control of the recess depth
Solution Approach 2:
The spacer layer acts as an intermediary material between the etchant and the gate structure. It mediates the interaction by providing a controlled interface that allows the etching process to proceed with high precision while protecting the sensitive gate structure from direct exposure to the etchant
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the manufacturing of TFETs with reduced power consumption and increased switching speed, potentially achieving sub-thermionic subthreshold slopes, and allows for flexible material choices and CMOS-compatible processes, enhancing the miniaturization and performance of FET structures.
Implementation Method 1
The spacer layer includes a lower etch rate than the first semiconductor structure in response to being etched with a predetermined etchant
Data Source
AI summary
The present disclosure relates to a method for fabricating a field-effect transistor structure on a substrate. The method includes forming a first semiconductor structure on the substrate, forming above the first semiconductor structure a gate structure that comprises a spacer layer laterally terminating the gate structure and has a lower etch rate than the first semiconductor structure with respect to a predetermined etchant, forming an undercut below the spacer layer by recessing the first semiconductor structure using the etchant, the undercut extending laterally below the spacer layer by not more than the thickness of the spacer layer, forming on the first semiconductor structure a second semiconductor structure filling the undercut, and forming a third semiconductor structure above the first semiconductor structure, wherein one of the second and third semiconductor structures forms the source of the field-effect transistor structure and the other one forms the drain.