SRAM Read Circuit Using TFET for Lower Energy

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional SRAM memory cells rely on MOSFETs for reading, which have higher energy consumption and lower sensitivity compared to tunneling field-effect transistors (TFETs).

Innovation Solution

Incorporating at least one tunneling field-effect transistor (TFET) into the read circuit of the SRAM memory cell, with its gate connected to the storage node and drain connected to the read bit line, allowing for reduced energy consumption and improved sensitivity by utilizing the TFET's lower sub-threshold swing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If MOSFET is used as the reading transistor in SRAM memory cell, then the device is easier to manufacture with conventional processes, but the energy consumption is higher and sensitivity is lower

Engineering Contradiction:
Improveenergy consumptionVSAvoidmanufacturing ease
Core Design Contradiction:
Use of energy by moving objectVSEase of manufacture

Solution Approach 1:

The patent changes the fundamental operating parameter of the reading transistor from MOSFET to TFET, exploiting the TFET's lower sub-threshold swing parameter to achieve reduced energy consumption while maintaining compatibility with conventional semiconductor manufacturing processes

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent substitutes the MOSFET reading transistor with a TFET reading transistor, replacing the conventional field-effect mechanism with a tunneling-based mechanism that operates at lower voltages and consumes less energy

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Measurement precision

If MOSFET is used as the reading transistor in SRAM memory cell, then the device structure is simpler and easier to fabricate, but the sensitivity for data retrieval is lower

Engineering Contradiction:
ImprovesensitivityVSAvoiddevice complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent changes the transistor type from MOSFET to TFET, utilizing the TFET's superior sub-threshold swing parameter to enhance sensitivity in detecting stored data states, while the overall device structure remains comparable to conventional SRAM designs

Inventive Principle:
Principle #35Parameter changes

3Loss of energy

If conventional SRAM read circuit is used, then the circuit design is simpler, but the power consumption is higher

Engineering Contradiction:
Improvepower consumptionVSAvoidcircuit complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent modifies the read circuit by replacing the MOSFET reading transistor with a TFET, exploiting the TFET's lower operating voltage and reduced sub-threshold swing to minimize power consumption during read operations while maintaining a relatively simple circuit architecture

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The use of TFETs in the read circuit reduces energy consumption and enhances the sensitivity of the memory cell, enabling more accurate data retrieval with lower power usage.

Implementation Method 1

at least one tunneling field-effect transistor (TFET), the gate of the tunneling field-effect transistor is electrically connected to the first storage node of the SRAM cell

Methodology Applied
Scientific EffectQuantum tunneling:

Data Source

PatentUS10157662B1Static random access memory cell, layout pattern and operation method thereof
Publication Date: 2018.12.18 UNITED MICROELECTRONICS CORP
  • US10157662B1 patent drawing
  • US10157662B1 patent drawing
  • US10157662B1 patent drawing

AI summary

The present invention provides a memory cell. The memory cell includes a static random access memory (SRAM) cell located on a substrate. The SRAM cell includes a first storage node. At least one tunneling field-effect transistor (TFET), the gate of the tunneling field-effect transistor is electrically connected to the first storage node of the SRAM cell. A read bit line (RBL) electrically connected the drain of the TFET. A read terminal which is connected to a read port voltage (Vrp) and electrically connects to a source of the TFET.