TFET Test Device with Dual-Source Drain Configuration
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Solution Overview
Problem
The increasing power consumption and operating speed of semiconductor devices, particularly MOSFETs, have reached a limit, necessitating the evaluation of alternative technologies like tunneling field effect transistors (TFETs) for reduced standby current, but reliable evaluation methods are lacking for TFETs.
Innovation Solution
A semiconductor device design that allows for intentional stress application and performance evaluation, sharing a channel layer between MOSFET and TFET modes, using a dual-source and dual-drain configuration with a controller to selectively form channels and apply voltage for stress simulation, enabling reliability analysis similar to MOSFET evaluation methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If MOSFET operating speed and integration are increased according to Moore's Law, then processing capability is improved, but power consumption increases greatly
Solution Approach 1:
The patent changes the fundamental operating principle of the transistor from thermal carrier excitation (MOSFET) to quantum tunneling (TFET). By adjusting the band alignment and tunneling barrier parameters, the device achieves low standby current while maintaining operational speed, directly resolving the power-speed contradiction
Solution Approach 2:
The patent utilizes band-to-band tunneling, which is a quantum mechanical phase transition phenomenon. Electrons tunnel directly from the valence band to the conduction band through the forbidden band, enabling current flow with minimal energy dissipation and eliminating the need for thermal excitation
2Use of energy by moving object
If TFET is used to reduce standby current, then power consumption is reduced, but reliability evaluation capability is insufficient
Solution Approach 1:
The patent designs a multi-functional test device that can evaluate both MOSFET and TFET characteristics using the same physical structure. The device includes test circuits that can selectively apply different voltage configurations to characterize either transistor type, enabling comprehensive reliability evaluation for TFETs while maintaining the power consumption benefits
Solution Approach 2:
The patent segments the test device into independent functional modules: a TFET under test, reference transistors, and separate test circuits for different characterization modes. This segmentation allows independent optimization of each module and enables systematic reliability evaluation through modular testing approaches
3Measurement precision
If a separate test device is designed for TFET reliability evaluation, then evaluation accuracy is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal test device structure that can evaluate both MOSFET and TFET characteristics. By using the same physical device with reconfigurable voltage applications and selective circuit connections, the patent achieves high evaluation accuracy for TFETs without requiring a completely separate complex test device
Solution Approach 2:
The patent merges the TFET test functions with existing MOSFET test device architectures. The test circuits for threshold voltage, mobility, and other parameters are combined into a single integrated device, reducing overall complexity while maintaining measurement precision through unified characterization methods
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for detailed characterization and reliability evaluation of TFETs, enhancing the assessment of their performance and longevity, facilitating the transition from MOSFETs to TFETs by ensuring safe and efficient operation.
Implementation Method 1
applying stimulation for forming stress on a surface between at least one of a first source layer, a first drain layer, a second source layer, and a second drain layer and a gate insulating layer to the semiconductor device
Data Source
AI summary
A semiconductor device for evaluating characteristics of a transistor is provided. The semiconductor device includes a substrate, an active area defined on the substrate, an insulated gate configured to be formed on the active area, a first source layer and a first drain layer configured to be formed on the active area in a first two-way direction of the gate, and a second source layer and a second drain layer configured to be formed on the active area in a second two-way direction of the gate. The first source layer, the first drain layer, and the second drain layer are formed as a first conductive type. The second source layer is formed as a second conductive type.