Thin-Film Resistor Module With Top-Side Interconnects
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Solution Overview
Problem
The existing methods for manufacturing thin-film resistors (TFRs) require multiple mask layers, are limited by annealing temperature, and are not suitable for high-performance analog designs with aluminum interconnects, while also facing challenges in achieving a near 0 ppm temperature coefficient of resistance (TCR).
Innovation Solution
The development of a damascene chemical mechanical planarization (CMP) process for forming TFR modules with top-side aluminum interconnects using a single added mask layer, allowing for annealing of the TFR element before forming the metal interconnects and removing vertically-extending ridges to improve TCR performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional TFR manufacturing processes are used, then multiple mask layers are required to create TFR heads, TFRs, and TFR vias, but this increases device complexity and manufacturing cost
Solution Approach 1:
The patent combines the formation of TFR heads and TFR structures into a single damascene process step. The metal layer is deposited over the entire wafer surface, and a single etch process selectively removes metal to form both TFR heads in dielectric regions and TFR structures in resistor regions, eliminating the need for separate mask layers for each component type.
Solution Approach 2:
The metal layer serves multiple functions simultaneously: it forms TFR heads for electrical connection, creates TFR structures as conductive elements, and provides interconnect functionality. This multi-functional approach allows a single deposition and patterning process to accomplish what previously required multiple specialized steps.
2Manufacturing precision
If annealing is performed after forming metal interconnects, then TCR can be adjusted, but the annealing temperature is limited by the metal interconnect material
Solution Approach 1:
The patent performs annealing of the TFR element before depositing and patterning the metal interconnect layer. This preliminary annealing allows the use of high temperatures (e.g., 400-600°C) to precisely control the temperature coefficient of resistance (TCR) without being constrained by the metal interconnect material's temperature limits, since the metal layer is added afterward.
3Manufacturing precision
If vertically-extending TFR ridges are present, then the TFR structure is formed, but these ridges negatively affect TCR performance
Solution Approach 1:
The patent removes or reduces the vertically-extending TFR ridges from the final structure. After the damascene process forms the TFR elements, an additional etch or planarization step is used to remove the excessive ridge material that extends vertically from the dielectric surface, leaving a flatter TFR structure that does not degrade TCR performance.
4Reliability
If copper interconnect is used, then lower resistivity and high electro-migration resistance are achieved, but traditional photoresist masking and plasma etching are difficult to manufacture
Solution Approach 1:
The patent replaces traditional photoresist masking and plasma etching processes with a damascene approach that uses conformal metal deposition followed by selective removal. This substitution allows copper interconnect to be manufactured using processes that are more compatible with copper's properties, avoiding the difficulties associated with traditional aluminum-based patterning methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of mask layers required, enables high-temperature annealing for precise TCR control, and enhances the performance of TFR modules by eliminating ridges that affect TCR, resulting in improved reliability and cost-effectiveness for TFRs in both copper and aluminum BEOL applications.
Implementation Method 1
damascene chemical mechanical planarization (CMP) process for forming TFR modules
Implementation Method 2
enables high-temperature annealing for precise TCR control
Data Source
AI summary
A method for manufacturing a thin film resistor (TFR) module in an integrated circuit (IC) structure is provided. A TFR trench may be formed in an oxide layer. A resistive TFR layer may be deposited over the structure and extending into the trench. Portions of the TFR layer outside the trench may be removed by CMP to define a TFR element including a laterally-extending TFR bottom region and a plurality of TFR ridges extending upwardly from the laterally-extending TFR bottom region. At least one CMP may be performed to remove all or portions of the oxide layer and at least a partial height of the TFR ridges. A pair of spaced-apart metal interconnects may then be formed over opposing end regions of the TFR element, wherein each metal interconnect contacts a respective upwardly-extending TFR ridge, to thereby define a resistor between the metal interconnects via the TFR element.