TFT Active Layer a-Si p-Si Segmentation for Leakage Reduction
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Solution Overview
Problem
Current AMOLED back plate production faces challenges with high leakage current due to the limitations of existing thin film transistor (TFT) technologies, particularly the p-Si layer's mobility and defects, which require additional processing steps and hardware limitations, making it difficult to achieve mass production of large-channel TFTs.
Innovation Solution
The proposed solution involves a thin film transistor (TFT) structure with an active layer comprising alternating a-Si and p-Si areas, where the a-Si areas are either at the center or symmetrically positioned between the source and drain, and the p-Si areas are formed through selective laser annealing, allowing for reduced leakage current and simplified production processes by eliminating the need for additional a-Si layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a p-Si layer is used in the TFT channel area to achieve high mobility, then the mobility rate increases to 5-20 cm2/V·s, but the leakage current becomes large due to electron penetration through the channel
Solution Approach 1:
The patent applies local quality by creating different silicon phases in different regions of the active layer. Specifically, the active layer includes both amorphous silicon (a-Si) regions with high resistance and polycrystalline silicon (p-Si) regions with high mobility. The a-Si regions are positioned at the source and drain contacts to block leakage current, while the p-Si region in the channel area provides high carrier mobility for efficient transistor operation.
2Object-generated harmful factors
If an additional a-Si layer is deposited on the p-Si and SiO2 island to reduce leakage current, then the leakage current decreases, but the technological complexity increases due to one more production step
Solution Approach 1:
The patent merges the functions of multiple layers into a single integrated active layer structure. Instead of having separate p-Si and a-Si layers that require multiple deposition and processing steps, the invention creates a unified active layer containing both a-Si regions (for leakage blocking) and p-Si regions (for high mobility) in a single structure, simplifying the manufacturing process while achieving both low leakage and high performance.
3Speed
If selective laser annealing is used to form p-Si areas, then the mobility rate increases, but the effective channel length is limited to about 1000 micrometers due to laser spot length constraints
Solution Approach 1:
The patent segments the active layer into multiple functional regions: a-Si regions at the source and drain contacts for leakage blocking, and a p-Si region in the channel area for high mobility. This segmentation allows the laser annealing process to be applied selectively to create the p-Si channel region while maintaining the a-Si contact regions, enabling the structure to support longer channel lengths beyond the laser spot limitation by using multiple laser passes or selective area annealing.
4Length of moving object
If a large-channel TFT with length greater than 1500 micrometers is needed for Gate driver On Array design, then the design requirements are met, but mass production becomes difficult due to laser effective spot length limitation
Solution Approach 1:
The patent applies local quality by creating distinct a-Si and p-Si regions within the active layer, where the a-Si regions are positioned at the source and drain contacts to provide high resistance and block leakage current, while the p-Si region in the channel area provides high carrier mobility. This localized functional differentiation allows the TFT to achieve both low leakage and high performance in large-channel configurations suitable for Gate driver On Array designs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces leakage current and technical complexity, enabling the production of large-channel TFTs beyond the limitations of existing laser spot lengths, facilitating mass production and improving TFT stability and design flexibility.
Implementation Method 1
the p-Si layer is made by using an MLA regional laser annealing technology, and high position accuracy laser annealing is selectively performed for the a-Si in the TFT channel area using a laser source beam
Implementation Method 2
performing laser radiation on one or multiple positions of the a-Si layer to form a p-Si area
Data Source
AI summary
The present disclosure provides a method for making a thin film transistor (TFT), a TFT, a back plate and a display device. The TFT includes: a gate electrode, a source, a drain, a dielectric layer and an active layer on the dielectric layer. The active layer includes at least one a-Si area and at least one p-Si area. This can reduce leakage current and reduce the technical complexity of the large-channel TFT.