Thin Film Transistor Active Layer Asymmetry for Alignment Tolerance
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Solution Overview
Problem
Existing thin film transistors face challenges in maintaining precise alignment between the gate, source, drain, and active layers, leading to changes in the channel width-to-length ratio, which affects the display quality of display devices.
Innovation Solution
The active layer is designed with two sides arranged in parallel, each forming a 45° acute angle with the drain, ensuring the channel width remains constant even with alignment deviations, and additional extension portions and chamfers are used to prevent collisions and maintain capacitance and display stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional rectangular active layer design is used, then manufacturing process is simple, but alignment deviation changes channel width-to-length ratio affecting display quality
Solution Approach 1:
The active layer is designed with an asymmetric shape where the width at the source and drain ends is greater than the width at the middle portion. Specifically, the active layer width at the source end and drain end is W1, while the width at the middle portion is W2, where W1 > W2. This asymmetric geometry compensates for alignment deviations during manufacturing, ensuring that the effective channel width-to-length ratio remains consistent even when layer alignment varies, thereby improving display quality without requiring extremely precise alignment processes
2Manufacturing precision
If alignment precision between layers is increased, then channel width-to-length ratio is maintained, but manufacturing complexity and cost increase
Solution Approach 1:
The invention changes the geometric parameters of the active layer from a traditional rectangular shape to a shape with varying width along its length. The width parameter W(x) changes continuously or in steps from W1 at the ends to W2 in the middle portion. This parameter modification allows the structure to tolerate alignment variations up to a certain threshold while maintaining consistent electrical characteristics, thereby reducing the need for extremely tight alignment tolerances and simplifying the manufacturing process
Data Source
AI summary
The present disclosure provides a thin film transistor, an array substrate, a display panel and a display device. The thin film transistor comprises a gate layer, a source and a drain located on the gate layer, and an active layer located on the source and the drain. The active layer is electrically connected to the source and the drain. The active layer comprises two sides arranged in parallel, and each side forms an acute angle of 45° with a face of the drain facing the source.