Thin Film Transistor Active Layer Width Optimization
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Solution Overview
Problem
Conventional thin film transistors have a small on-state current due to the equal width of the active layer and gate, and reducing the gate width can lead to disconnections.
Innovation Solution
A thin film transistor design where the active layer's width is smaller than the gate width, with a buffer layer and conducting layer configuration that allows the gate's projection to cover the active layer's projection, and includes a thin region in the buffer layer to facilitate carrier flow, enabling a smaller active layer width without disconnections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the width of the active layer is reduced to increase on-state current, then the on-state current increases, but the gate may become disconnected
Solution Approach 1:
The buffer layer is divided into a first buffer layer and a second buffer layer with different thicknesses. The first buffer layer has a first thickness and the second buffer layer has a second thickness smaller than the first thickness, creating a segmented structure that allows the gate to be formed over the thinner region without disconnection while maintaining proper electrical characteristics
Solution Approach 2:
Different regions of the buffer layer are given different thicknesses to serve different functions. The first buffer layer region provides adequate thickness for electrical isolation and stability, while the second buffer layer region provides reduced thickness to allow the gate to extend beyond the active layer width without causing disconnection, thus enabling the active layer width to be reduced while maintaining reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly increases the on-state current of the thin film transistor while being simple and suitable for industrial production, allowing the active layer width to be reduced without affecting the transistor's performance.
Implementation Method 1
a buffer layer on a surface of the substrate... an orthographic projection of the gate on the substrate covers an orthographic projection of the active layer on the substrate
Data Source
AI summary
A thin film transistor (10) may include a substrate (100); a buffer layer (300) on a surface of the substrate (100); an active layer (400) on a surface of the buffer layer (300) opposite from the substrate (100); a gate insulating layer (500) on a surface of the active layer (400) opposite from the substrate (100), and a gate (600) on a surface of the gate insulating layer (500) opposite from the substrate (100). A width of the active layer (400) may be smaller than a width of the gate (600), and an orthographic projection of the gate (600) on the substrate (100) may cover an orthographic projection of the active layer (400) on the substrate (100).