Thin Film Transistor Adjacent Layer Electrode Aperture Ratio
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Solution Overview
Problem
Conventional array substrates for display panels using low temperature poly-silicon materials face challenges in thermal processing, leading to reduced aperture ratio due to the necessity of forming via holes for connecting source and drain electrodes with the active layer pattern, which compromises pixel region efficiency.
Innovation Solution
The thin film transistor design positions the source and drain electrodes in an adjacent layer to the active layer pattern, eliminating the need for via holes and directly connecting them, thereby improving the aperture ratio by simplifying the manufacturing process and reducing the number of required patterning steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If via holes are formed to connect source and drain electrodes with the active layer pattern, then electrical connections are established, but the aperture ratio of the pixel region is reduced
Solution Approach 1:
The source and drain electrodes are positioned in an adjacent layer to the active layer pattern, transitioning from a planar connection method (via holes) to a three-dimensional stacked configuration. This dimensional change allows direct electrical connection without penetrating the pixel region, thereby maintaining aperture ratio while ensuring reliable electrical connectivity.
Solution Approach 2:
The connection method is extracted from the traditional via-hole approach and replaced with a direct adjacent-layer configuration. By removing the via hole formation step, the patent eliminates the aperture ratio reduction while maintaining the essential electrical connection function between electrodes and active layer.
2Reliability
If via holes are formed for connecting electrodes, then electrical connections are achieved, but the manufacturing process complexity increases
Solution Approach 1:
The via hole formation process is completely removed from the manufacturing sequence. By positioning source and drain electrodes in an adjacent layer that directly contacts the active layer pattern, the patent eliminates the complex multi-step via hole creation process (drilling, filling, planarization) while maintaining reliable electrical connections.
Solution Approach 2:
The manufacturing process is segmented into distinct layer formation steps, where the active layer pattern and source/drain electrodes are formed in separate adjacent layers. This segmentation allows each layer to be optimized independently without the need for via hole integration, simplifying the overall manufacturing process.
Data Source
AI summary
Embodiments of the invention provide a thin film transistor, an array substrate and a manufacturing method thereof, and a display panel. The thin film transistor comprises: an active layer pattern, a source electrode, a drain electrode and a gate electrode. The gate electrode is positioned above the active layer pattern, the source electrode is connected with the active layer pattern, the drain electrode is connected with the active layer pattern, and the source electrode and the drain electrode are disposed in an adjacent layer of the active layer pattern.