Thin-Film Transistor Substrate Alignment Electrodes
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Solution Overview
Problem
Existing thin-film transistor manufacturing methods face challenges in achieving symmetrical lightly doped drain (LDD) regions due to alignment errors during the doping process, which can lead to asymmetrical LDD structures and reduced reliability of the transistors, especially as transistors are miniaturized.
Innovation Solution
A method involving the formation of alignment electrodes on either side of the gate electrode, which compensates for mask alignment errors by adjusting the development of the photoresist layer, ensuring symmetrical LDD regions through precise doping processes using different impurity concentrations and masks, thereby maintaining transistor reliability even at smaller sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional doping processes are used without alignment electrodes, then the manufacturing process is simpler, but alignment errors occur during doping which lead to asymmetrical LDD regions and reduced transistor reliability
Solution Approach 1:
Alignment electrodes are introduced as intermediary structures between the gate electrode and the doping process. These electrodes serve as reference markers that enable precise alignment of the photoresist mask during doping, thereby eliminating alignment errors and ensuring symmetrical LDD regions without significantly complicating the overall manufacturing process
Solution Approach 2:
The alignment electrodes are formed in advance before the doping process. By preparing these reference structures beforehand, the patent ensures that subsequent doping operations can be accurately aligned, preventing asymmetrical LDD formation and improving transistor reliability before the actual doping occurs
2Area of moving object
If transistors are miniaturized to reduce device size, then the integration density increases, but alignment errors become more critical and LDD symmetry becomes harder to maintain
Solution Approach 1:
The alignment electrodes act as intermediary reference structures that become increasingly important as transistors are miniaturized. These electrodes provide fixed reference points that enable precise mask alignment even at smaller dimensions, ensuring that LDD regions remain symmetrical despite the reduced transistor area and tighter spacing requirements
3Productivity
If asymmetrical LDD regions are formed due to alignment errors, then the manufacturing process is faster, but hot carrier generation and punch-through characteristics increase, reducing transistor performance
Solution Approach 1:
The alignment electrodes serve as intermediary reference structures that enable rapid yet precise alignment during doping. By providing fixed reference points, they allow the doping process to proceed quickly without sacrificing alignment accuracy, thus maintaining LDD symmetry and preventing hot carrier generation and punch-through effects while preserving manufacturing efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method ensures symmetrical LDD regions are formed, enhancing the reliability of thin-film transistors by reducing hot carrier generation and punch-through characteristics, even with reduced channel lengths, thus addressing the issue of alignment errors and maintaining performance during miniaturization.
Implementation Method 1
exposing and developing the photoresist layer by using a first mask having a first pattern
Implementation Method 2
A first doping process is performed by doping the semiconductor pattern layer with a first impurity by using the cover layer as a mask
Data Source
AI summary
Provided is a method of manufacturing a thin-film transistor substrate, the method includes forming a semiconductor pattern layer on a substrate. A first insulating film is formed on the semiconductor pattern layer. A metal pattern layer including a gate electrode and first and second alignment electrodes respectively spaced apart from two sides of the gate electrode is formed on the first insulating film. A cover layer covering the gate electrode is formed. The first and second alignment electrodes are removed. A first doping process is performed by doping the semiconductor pattern layer with a first impurity by using the cover layer as a mask. The cover layer is removed. A second doping process is performed by doping the semiconductor pattern layer with a second impurity having a lower impurity concentration than the first impurity by using the gate electrode as a mask.