TFT Array 4M Process Oxygen Ashing Residue Reduction
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Solution Overview
Problem
Conventional 4M production processes for TFT arrays suffer from residues of amorphous silicon and heavily doped silicon on the edges of the second metal layer, affecting optical stability, electrical performance, aperture ratio, power consumption, and reliability of thin-film transistors.
Innovation Solution
An optimized 4M production process is introduced, which includes additional oxygen ashing steps in the etching operations to reduce these residues, conducted within the same chambers as the original process, using gray-tone or half-tone masks, and employing specific materials and deposition methods for the gate, insulation, and active layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional 4M production process with half-tone mask or gray-tone mask is used, then the production efficiency is improved and 4M process is achieved, but residues of amorphous silicon and heavily doped silicon remain on edges of the second metal layer
Solution Approach 1:
The patent segments the etching process into multiple distinct steps: a first etching step to form the active layer island structure, followed by a second etching step to form the source and drain electrodes. This segmentation allows each etching step to be optimized independently, with the first step creating precise island structures and the second step forming clean electrode edges without silicon residues.
Solution Approach 2:
The patent performs preliminary patterning of the active layer into island structures before forming the source and drain electrodes. This preliminary action ensures that the active layer is properly configured and positioned, allowing subsequent etching steps to cleanly define the electrode edges without leaving residues.
2Manufacturing precision
If additional oxygen ashing steps are added to reduce residues, then the manufacturing precision and cleanliness are improved, but the process complexity increases
Solution Approach 1:
The patent combines the oxygen ashing function into the existing etching chamber operations. The first and second etching steps are performed in the same plasma environment, where oxygen radicals naturally present during the etching process simultaneously perform the ashing function to remove photoresist and clean edges, eliminating the need for separate oxygen ashing equipment or steps.
Solution Approach 2:
The etching chamber is designed to perform multiple functions: it conducts the primary etching of metal layers to form patterns, and simultaneously performs oxygen ashing to remove photoresist residues and clean edges. This multi-functionality reduces overall process complexity by consolidating operations into a single piece of equipment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves optical stability, electrical performance, aperture ratio, and reliability, reduces power consumption, and eliminates heavily doped residues by approximately 0.9 um in the channel area and 1 um in the amorphous silicon area, enhancing the overall performance of the TFT array substrate.
Implementation Method 1
subjecting the photoresist layer to exposure and development; conducting a first wet etching operation to pattern the source/drain layer to form metal line structures of source and drain areas and an active area; conducting a first dry etching operation to form an active layer island structure
Implementation Method 2
conducting a first oxygen ashing operation to reduce a size of trailing of the active layer on edges of the source/drain metal layer; conducting a second oxygen ashing operation to reduce a thickness of the photoresist layer
Implementation Method 3
conducting a first dry etching operation to form an active layer island structure; conducting a second dry etching operation to etch the active layer so as to form a thin-film transistor structure
Implementation Method 4
conducting a first wet etching operation to pattern the source/drain layer to form metal line structures of source and drain areas and an active area; conducting a second wet etching operation to pattern a source and a drain
Data Source
AI summary
The present invention provides a TFT array manufacturing method of an optimized 4M production process. The method includes: Step 10, in a first mask-based process, making a gate layer on a glass substrate and patterning the gate layer; Step 20, in a second mask-based process, subjecting the photoresist layer to exposure and development; conducting a first wet etching operation to pattern the source/drain layer; conducting a first oxygen ashing operation to reduce a size of trailing of the active layer on edges of the source/drain metal layer; conducing a first dry etching operation to form an active layer island structure; conducting a second oxygen ashing operation to expose portions of the source/drain layer in the channel area; conducting a second wet etching operation to pattern a source and a drain; conducting a third oxygen ashing operation to reduce trailing of the contact layer; and conducting a second dry etching operation to etch the active layer; Step 30, in a third mask-based process, making a passivation layer followed by patterning; and Step 40, in a fourth mask-based process, making a transparent electrode layer followed by patterning. The present invention allows for, on the basis of an existing production process, successful elimination of heavily doped residue in a channel area (by reducing around 0.9 um) and reducing around 1 um in an amorphous silicon area.