Thin Film Transistor Array Substrate Aperture Design
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Solution Overview
Problem
Conventional liquid crystal display devices in FFS mode require multiple etching steps for aperture formation, leading to increased contact resistance and parasitic capacitance, which in turn increase power consumption and reduce adhesion of organic flattening films.
Innovation Solution
A thin film transistor array substrate design with a common electrode connected indirectly to the common wiring through multiple apertures in interlayer insulating films, reducing the aperture ratio and enhancing contact stability, while maintaining a thick insulating film on source wiring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple etching steps are executed to form apertures for connecting common electrode and pixel electrode to wirings, then electrical connections are established, but contact resistance increases and manufacturing complexity increases
Solution Approach 1:
The patent combines the formation of the first aperture (connecting common electrode to common wiring) and the second aperture (connecting pixel electrode to drain electrode) into a single simultaneous etching process. This merging of operations reduces the total number of etching steps from multiple sequential steps to one unified step, thereby reducing manufacturing complexity while maintaining reliable electrical connections with minimized contact resistance.
2Loss of energy
If a thick insulating film is formed on source wiring to shield electric field, then parasitic capacitance is reduced, but aperture ratio decreases
Solution Approach 1:
The patent applies the thick insulating film (flattening film) selectively only on the source wiring region where electric field shielding is needed to reduce parasitic capacitance. The film is not uniformly applied across the entire pixel region, allowing the aperture area to remain maximized in the pixel electrode region while still providing the necessary shielding function locally on the source wiring. This localized application resolves the contradiction between energy loss reduction and aperture ratio maintenance.
Data Source
AI summary
A pixel electrode is connected to a drain electrode of TFT via a first aperture formed on a second interlayer insulating film, a second aperture, which includes a bottom portion of the first aperture and is formed on a common electrode, and a third aperture, which is included in the bottom portion of the first aperture and is formed on a first interlayer insulating film and a third interlayer insulating film. The common electrode is connected to a common wiring via a fourth aperture formed on the second interlayer insulating film, and a fifth aperture that is included in a bottom portion of the fourth aperture and is formed on the first interlayer insulating film, and a contact electrode that is formed in the fourth aperture and the fifth aperture.