Thin Film Transistor Array Panel Capacitor Integration
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Solution Overview
Problem
The thickness and size of liquid crystal displays are increased by IC chips and capacitors on flexible printed circuit substrates, leading to increased manufacturing costs.
Innovation Solution
A thin film transistor array panel design where the driving capacitor is formed in the peripheral area by overlapping gate and data lines, allowing for a reduced size of the flexible printed circuits, with capacitors constructed from triple-layer structures to minimize resistance and maintain voltage consistency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If IC chips and capacitors are mounted on flexible printed circuit substrates, then the liquid crystal display can be assembled with standard components, but the thickness and size of the display are increased
Solution Approach 1:
The patent merges the capacitor structure with the gate and data line structures by forming both components using the same triple-layer conductor deposits and etching processes. The capacitor conductors are formed as integral parts of the same fabrication sequence that creates the gate and data lines, combining multiple functions into a unified structure that eliminates separate capacitor components and reduces overall display thickness.
Solution Approach 2:
The triple-layer conductor structure serves multiple functions simultaneously: it forms both the gate lines and data lines, and also creates the capacitor conductors. This multi-functional approach allows a single structural system to perform both signal transmission and energy storage functions, eliminating the need for separate capacitor mounting and reducing the display's overall volume.
2Adaptability or versatility
If multiple IC chips and capacitors are mounted on FPC substrates, then the display can achieve full functionality, but the size of the gate and data FPCs increases
Solution Approach 1:
The patent combines the capacitor functionality with the existing gate and data line structures on the FPC substrate. By forming capacitor conductors using the same material layers and fabrication processes as the signal lines, the design integrates energy storage directly into the signal transmission pathways, eliminating separate capacitor components and reducing the required FPC substrate area.
Solution Approach 2:
The patent utilizes the vertical stacking of triple-layer conductor structures to create capacitors in the thickness dimension rather than expanding capacitor footprints in the planar dimension. By forming overlapping conductor layers that serve as capacitor plates, the design moves the capacitor function into the vertical dimension, preserving FPC substrate area while maintaining full display functionality.
3Reliability
If more IC chips and capacitors are added to achieve full functionality, then the display performance is improved, but the manufacturing cost increases
Solution Approach 1:
The patent merges the fabrication processes for gates, data lines, and capacitors into a single integrated sequence. By using the same triple-layer conductor deposits and etching patterns to create all three components simultaneously, the design eliminates separate manufacturing steps for capacitor assembly, reducing process complexity and manufacturing cost while maintaining reliable display performance.
Solution Approach 2:
The universal triple-layer conductor structure performs multiple functions: signal transmission through gate and data lines, and energy storage through capacitor formation. This multi-functional design reduces the total number of distinct components and fabrication processes required, thereby reducing device complexity and manufacturing cost while achieving full display functionality.
Data Source
AI summary
A thin film transistor array panel includes an insulation substrate having a display area and a peripheral area, a gate line formed on the insulation substrate, a first capacitor conductor made of the same material as the gate line and formed in the peripheral area of the insulation substrate, a gate insulating layer formed on the gate line and the first capacitor conductor, a semiconductor layer formed on the gate insulating layer, a data line and a drain electrode formed on the semiconductor layer and formed in the display area of the insulation substrate, a second capacitor conductor formed of the same material as the data line and formed in the peripheral area of the insulation substrate, and a pixel electrode connected to the drain electrode. The first capacitor conductor and the second capacitor conductor overlap each other. Since the driving capacitor that has been formed on the FPC substrate in the prior art is formed in a peripheral area of the thin film transistor array panel, the FPC can be formed as one layer and a size of the FPC can be substantially reduced and thereby a slim and small-sized liquid crystal display can be produced.