TFT Array Panel Signal Line Contact Compensation

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Solution Overview

Problem

In liquid crystal displays (LCDs), the increasing size of the driver area and resistance differences between signal transmission lines due to varying lengths lead to signal delays and deteriorated display performance.

Innovation Solution

A thin film transistor array panel design with a substrate having a display area and peripheral areas, featuring first and second signal lines, connection lines, and an insulating layer with contact holes to connect the lines, where the sizes of exposed portions of the signal lines increase with distance from the driver, and data signal transmission lines with different contact sizes to reduce resistance differences.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the driver is disposed on the peripheral area of the lower panel, then the driving function is achieved, but the size of the TFT array panel increases

Engineering Contradiction:
Improvedriving functionVSAvoidpanel size
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The driver is extracted from the display area and disposed on the peripheral area, separating the driving function from the display function. This allows the display area to maintain its size while the driver occupies peripheral space, resolving the contradiction between achieving driving function and minimizing panel size increase.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The driver layout transitions from occupying display area to peripheral area, effectively moving the driver to a different spatial dimension (periphery vs. center). This dimensional repositioning allows the display area to remain maximized while still accommodating the driver functionality.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If signal transmission lines have different lengths, then connection flexibility is improved, but resistance differences increase causing signal delay

Engineering Contradiction:
Improveconnection flexibilityVSAvoidsignal transmission quality
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

Different compensation structures are applied to different signal lines based on their specific length and resistance characteristics. Signal lines with longer lengths receive larger contact holes for compensation, while shorter lines receive smaller contact holes. This localized quality adjustment balances the resistance across all signal lines, resolving the contradiction between connection flexibility and signal transmission quality.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The contact hole sizes are varied as a parameter to compensate for resistance differences in signal lines of different lengths. By changing the contact hole size parameter, the resistance is adjusted to achieve uniform signal transmission characteristics across all lines, maintaining both flexibility and reliability.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If contact hole sizes are increased for signal lines farther from the driver, then resistance differences are compensated, but manufacturing complexity increases

Engineering Contradiction:
Improveresistance balanceVSAvoidcontact hole fabrication
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The contact hole size is used as a controllable parameter that varies systematically based on distance from the driver. This parameter change approach allows for automated calculation and fabrication, where the size is adjusted in a predictable pattern rather than requiring complex individual design for each contact hole, thus maintaining ease of manufacture while achieving resistance balance.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS7787095B2Thin film transistor array panel and method of manufacturing the same
Publication Date: 2010.08.31 SAMSUNG DISPLAY CO LTD
  • US7787095B2 patent drawing
  • US7787095B2 patent drawing
  • US7787095B2 patent drawing

AI summary

A thin film transistor array panel including a substrate, a plurality of first signal lines formed on the substrate, a plurality of second signal lines, insulated from the first signal lines, which are formed on the substrate and which define an area of a display area by traversing the first signal lines, a driver disposed on a peripheral area, a plurality of connection lines, disposed on the peripheral area, which couple the driver to each of the first signal lines, and an insulating layer which insulate the first signal lines from the connection lines. The insulating layer includes a plurality of contact holes, portions of the first signal lines and the connection lines are connected through the contact holes, and sizes of exposed portions of the first signal lines exposed through the contact holes increase as respective distances from the contact holes to the driver increase.