TFT Array Substrate Copper Data Line Segmentation

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Solution Overview

Problem

In thin film transistor array substrates, the migration of copper (Cu) through insulating films leads to short-circuits between gate and source/drain electrodes, reducing the reliability and yield of display devices due to high ductility and resistance issues in signal lines.

Innovation Solution

A thin film transistor array substrate with a data line comprising multiple metal layers, including a low-resistance copper layer, and source and drain electrodes formed without the top copper layer to prevent Cu migration, enhancing reliability and yield by avoiding short-circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If a stacked structure including copper (Cu) is used in data lines to reduce resistance, then power consumption is reduced, but Through Migration of Cu occurs easily due to high ductility of Cu

Engineering Contradiction:
Improvepower consumptionVSAvoidThrough Migration resistance
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The data line is divided into multiple stacked metal layers, with Cu layers positioned at specific depths. The Cu layer is segmented from being the topmost layer, allowing differentiation between regions prone to migration and regions requiring low resistance. This segmentation enables the Cu layer to contribute to low resistance while reducing its exposure to stress and mechanical wear that cause Through Migration.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention transitions from a single-layer Cu structure to a multi-layer stacked structure, adding the vertical dimension. By positioning the Cu layer at a specific depth within the stack rather than at the surface, the patent utilizes the vertical dimension to protect the Cu from environmental factors and mechanical stress that cause Through Migration, while still maintaining electrical connectivity and low resistance.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Loss of energy

If source and drain electrodes include the Cu layer to maintain low resistance, then power consumption is reduced, but height difference causes weak insulating film formation and facilitates Cu migration

Engineering Contradiction:
Improvepower consumptionVSAvoidinsulating film uniformity
Core Design Contradiction:
Loss of energyVSManufacturing precision

Solution Approach 1:

The patent applies local quality by making the Cu layer present in the data line but absent from the source and drain electrodes. This localized differentiation allows the data line to have low resistance where Cu is present, while the source and drain electrodes have uniform height and good insulating film formation where Cu is excluded. Each region is optimized for its specific functional requirements.

Inventive Principle:
Principle #3Local quality

3Reliability

If Cu layer is included in all conductive structures, then low resistance is achieved, but short-circuits occur due to Cu migration through insulating films

Engineering Contradiction:
Improveshort-circuit preventionVSAvoidresistance
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent extracts the Cu layer from the source and drain electrode structures while retaining it in the data line. This selective removal eliminates the height difference problem and prevents Cu migration from these electrodes, thereby preventing short-circuits. The Cu layer remains in the data line to maintain low resistance, achieving a balance between reliability and energy efficiency.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentEP2808893B1Thin film transistor array substrate and method of manufacturing the same
Publication Date: 2018.10.24 LG DISPLAY CO LTD
  • EP2808893B1 patent drawingFigure 1
  • EP2808893B1 patent drawingFigure 2
  • EP2808893B1 patent drawingFigure 3

AI summary

A thin film transistor (TFT) array substrate is disclosed. The TFT array substrate includes a gate line (6L), a first gate electrode (6E1) branched from the gate line (6L), a gate insulating film (102) formed over the substrate (101), an active layer (ACT) formed on the gate insulating film (102), a data line (DL) formed to comprise a plurality of metal layers including a first metal layer and a second metal layer formed of copper (Cu), a source electrode (SE) formed on the gate insulating film (102) to comprise the remaining metal layer excluding the second metal layer among the plurality of the metal layers, and a drain electrode (DE) formed on the gate insulating film (102) to comprise the remaining metal layer excluding the second metal layer among the plurality of the metal layers.