Thin Film Transistor Array Panel Etching Method
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Solution Overview
Problem
Conventional etching processes in thin film transistor array panels often result in skew and under-cut issues due to isotropic etching, leading to semiconductor layer protrusion beyond the metal layer boundaries, which affects display resolution and requires increased design margins.
Innovation Solution
A manufacturing method involving sequential etching operations using multiple masks to form semiconductor and metal layers with precise boundaries, ensuring the semiconductor layer does not protrude more than 0.5 um beyond the metal layer edges, and using a wet etching method to avoid isotropic etching-related issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If wet etching method is used, then etching rate is improved, but isotropic etching causes skew and under-cut generation leading to semiconductor layer protrusion
Solution Approach 1:
The patent segments the etching process into multiple sequential steps with different masks. First, a preliminary pattern is formed, then a main pattern is formed with precise alignment. This segmentation allows the use of wet etching for high rate while achieving precise boundaries through multiple controlled steps rather than a single isotropic etching step.
Solution Approach 2:
The patent performs preliminary patterning to form a preliminary pattern that defines the future boundary. This preliminary action creates a reference structure that guides subsequent etching steps, ensuring that the final pattern achieves precise boundaries even when using wet etching methods with higher rates.
2Device complexity
If single mask process is used, then manufacturing complexity is reduced, but layer boundary alignment precision deteriorates
Solution Approach 1:
The patent divides the patterning process into multiple mask steps, segmenting the single complex masking operation into sequential simpler steps. Each mask step focuses on forming a specific portion of the final pattern, which simplifies individual mask design and alignment while achieving high overall precision through the segmented approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces skew and under-cut generation, maintaining precise layer boundaries and improving display resolution by ensuring the semiconductor layer aligns with the metal layer edges, thus enhancing the manufacturing efficiency and quality of thin film transistor array panels.
Implementation Method 1
a wet etching method to avoid isotropic etching-related issues
Implementation Method 2
If etching process is performed on an oxide semiconductor formed of titanium or copper by using a dry etching method
Data Source
AI summary
A method for manufacturing a thin film transistor array panel includes forming a gate line and a gate electrode protruding from the gate line on a substrate; forming a gate insulating layer on the gate line and the gate electrode; depositing sequentially a semiconductor material and a metal material on the gate insulating layer; performing a first etching operation on the semiconductor material and the metal material using a first mask to form a semiconductor layer and a metal layer, the metal layer including a data line, a source electrode, and a drain electrode, in which the drain electrode protrudes from the data line, and the source electrode and the drain electrode having an integral shape; and performing a second etching operation on the metal layer using a second mask to divide the source electrode and the drain electrode.