Thin Film Transistor Array Substrate Gate Electrode Adhesion
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Solution Overview
Problem
In the manufacturing of organic light emitting display devices, existing photolithography processes often result in undercuts and adhesion issues during patterning of gate electrodes and signal wirings, leading to defects such as step coverage deterioration and short circuits, and require complex multi-mask processes increasing manufacturing costs and time.
Innovation Solution
A thin film transistor array substrate design with a gate electrode directly contacting a first insulation layer, formed from multiple metal layers without transparent conductive oxide, and a pixel electrode connected via an opening in a second insulation layer, allowing for continuous doping of ion impurities in the semiconductor layer, simplifying the manufacturing process to six mask steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography process is used to form fine patterns on substrate, then pattern transfer capability is improved, but undercut formation and adhesion issues occur during gate electrode patterning
Solution Approach 1:
The patent removes the transparent conductive oxide layer that was previously used as part of the gate electrode structure. By extracting this problematic layer, the invention eliminates the undercut formation and adhesion issues that occurred during photolithography patterning, while still achieving the desired electrical functionality through alternative structural arrangements.
Solution Approach 2:
Instead of forming the gate electrode with transparent conductive oxide and then patterning it (which caused adhesion problems), the invention inverts the approach by using metal layers directly and adjusting the patterning sequence. The gate electrode is formed through a modified process where metal layers are deposited and patterned after the insulation layers are in place, preventing the adhesion failures that occurred with the conventional approach.
2Manufacturing precision
If complex multi-mask processes are used to prevent defects, then manufacturing precision is improved, but manufacturing cost and time increase
Solution Approach 1:
The patent merges multiple process steps into fewer mask operations. By combining the formation of insulation layers and gate electrodes into an integrated process sequence with only six mask steps, the invention achieves high manufacturing precision without requiring the complex multi-mask processes that would otherwise be needed to prevent defects.
Solution Approach 2:
The invention performs preliminary actions by pre-forming the insulation layers with specific structures before depositing metal layers. This preliminary preparation of the substrate and insulation layers enables subsequent gate electrode formation without requiring additional corrective mask steps, thereby reducing overall process complexity while maintaining high precision.
3Reliability
If gate electrode is formed with transparent conductive oxide and metal layers, then electrical conductivity is improved, but step coverage deterioration occurs during patterning
Solution Approach 1:
The patent extracts the transparent conductive oxide layer from the gate electrode structure. By removing this layer that caused step coverage deterioration during patterning, the invention achieves clean, precise pattern formation while maintaining electrical conductivity through the metal layers alone, which provide sufficient conductive performance without the patterning problems associated with transparent conductive oxides.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design prevents undercuts and adhesion issues, improves device characteristics, enhances signal transfer quality, and reduces manufacturing complexity and costs by simplifying the process while maintaining high aspect ratios and electrostatic capacitance.
Implementation Method 1
The first electrode may include a semiconductor doped with ion impurities. The semiconductor doped with ion impurities may be present continuously between the first electrode and the connection portion.
Implementation Method 2
a pixel electrode including a transparent conductive oxide, the pixel electrode being on a portion of the first insulation layer extending from the thin film transistor
Implementation Method 3
an organic light emitting layer on the pixel electrode
Data Source
AI summary
A thin film transistor array substrate includes a thin film transistor including an activation layer, a gate electrode, source and drain electrodes, a first insulation layer between the activation layer and the gate electrode, and a second insulation layer between the gate electrode and the source and drain electrodes, a pixel electrode including a transparent conductive oxide, the pixel electrode being on a portion of the first insulation layer extending from the thin film transistor and being connected to one of the source and drain electrodes via an opening in the second insulation layer, a capacitor including a first electrode and a second electrode, the first electrode being on a same layer as the activation layer and including a transparent conductive oxide, and the second electrode being between the first and second insulation layers, and a third insulation layer covering the source and drain electrodes and exposing the pixel electrode.