TFT Array Substrate Fabrication Using Halftone Mask Patterning
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Solution Overview
Problem
The complexity and time-consuming nature of photolithography using masks in fabricating thin-film transistor (TFT) array substrates lead to process management difficulties and increased defect rates in producing active matrix flat panel displays.
Innovation Solution
A simplified method for fabricating a TFT array substrate involving the formation of an active layer, capacitor electrodes, gate and interlayer insulating films, and source and drain electrodes using a reduced number of masks, specifically employing a halftone mask for patterning, which reduces processing steps and enhances precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography using masks is used to form fine patterns in TFTs, then manufacturing precision is improved, but device complexity and processing time increase
Solution Approach 1:
The patent combines multiple photolithography steps into a single process by forming the gate electrode, source electrode, and drain electrode patterns simultaneously using one photoresist layer and one mask. This merging of steps reduces process complexity while maintaining the precision needed for fine pattern formation in TFTs.
Solution Approach 2:
The photoresist layer serves multiple functions: it defines the gate electrode pattern, the source electrode pattern, and the drain electrode pattern all in one application. This multi-functionality eliminates the need for separate photoresist applications and masks for each electrode, simplifying the overall fabrication process.
2Manufacturing precision
If photolithography using masks is used to form fine patterns in TFTs, then manufacturing precision is improved, but processing time increases
Solution Approach 1:
Multiple patterning operations that would traditionally require sequential processing are merged into a single photolithography step. The gate, source, and drain electrode patterns are all formed in one exposure and development cycle, dramatically reducing the total processing time while preserving pattern precision.
Solution Approach 2:
The patent performs preliminary patterning of all electrode regions in a single photoresist application before any etching or deposition steps. This preliminary action establishes all necessary patterns upfront, eliminating the need for subsequent re-patterning operations and reducing overall fabrication time.
3Manufacturing precision
If photolithography using masks is used to form fine patterns in TFTs, then manufacturing precision is improved, but process management difficulty increases
Solution Approach 1:
The patent merges the management of multiple photoresist processing steps into a single step, eliminating the need to track and manage separate exposure, development, and stripping operations for each electrode. This consolidation significantly improves process management ease while maintaining the precision required for TFT fabrication.
4Manufacturing precision
If photolithography using masks is used to form fine patterns in TFTs, then manufacturing precision is improved, but defect rate increases
Solution Approach 1:
By combining multiple photolithography steps into one, the patent eliminates multiple opportunities for defects to occur during photoresist application, exposure, development, and stripping. Fewer process steps mean fewer potential failure points, reducing the overall defect rate while maintaining the manufacturing precision needed for fine TFT patterns.
Data Source
AI summary
A thin-film transistor (TFT) array substrate comprises: a substrate; an active layer and a capacitor first electrode formed on the substrate; a gate insulating film formed on the substrate, the active layer and the capacitor first electrode; a gate electrode formed on the gate insulating film corresponding to the active layer and a capacitor second electrode formed on the gate insulating film corresponding to the capacitor first electrode; an interlayer insulating film formed on the gate insulating film, the gate electrode, and the capacitor second electrode; and a pixel electrode, a source electrode, and a drain electrode formed on the interlayer insulating film; wherein at least one of the source electrode and the drain electrode is formed on the pixel electrode. A method of fabricating the TFT array substrate is also disclosed.