Thin Film Transistor Array Panel Hillock Uniformity
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Solution Overview
Problem
The existing thin film transistor (TFT) technologies face challenges in achieving uniform hillock distribution during the crystallization process of polysilicon, leading to non-uniform characteristics such as deviations in threshold voltage, operation voltage distribution, and hysteresis, which affect the performance of TFTs in display devices.
Innovation Solution
A thin film transistor array panel design that includes a metal pattern positioned between the substrate and the buffer layer, where the metal pattern overlaps at least one of the source or drain regions of the semiconductor layer, acting as a start point for hillock formation, ensuring uniform hillock distribution across the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If polysilicon crystallization process is used to achieve high charge mobility, then charge mobility is improved, but hillock distribution becomes non-uniform causing deviations in threshold voltage and operation characteristics
Solution Approach 1:
A buffer layer is introduced as an intermediary between the metal pattern and the polysilicon layer. This buffer layer mediates the interaction between the metal pattern and polysilicon, enabling the metal pattern to serve as an effective hillock formation start point while preventing direct contact that would cause non-uniform hillock distribution. The buffer layer thus facilitates the beneficial effect of metal patterns on charge mobility while eliminating their harmful effect on hillock uniformity.
2Manufacturing precision
If metal pattern is positioned to overlap channel region to form hillocks, then hillock formation is improved, but threshold voltage deviation increases due to non-uniform hillock distribution
Solution Approach 1:
The invention applies local quality by positioning the metal pattern to overlap only the source or drain regions of the semiconductor layer, while deliberately excluding the channel region. This creates different functional zones: the source/drain regions contain hillocks formed from metal pattern start points, while the channel region maintains uniform thickness without metal-induced non-uniformities. This localized differentiation ensures both effective hillock formation and threshold voltage uniformity.
3Manufacturing precision
If buffer layer is positioned on metal pattern, then hillock distribution uniformity is improved, but device complexity increases due to additional layer
Solution Approach 1:
The buffer layer serves multiple functions simultaneously: (1) acts as a barrier preventing direct contact between metal pattern and polysilicon, (2) serves as a foundation for uniform polysilicon deposition, (3) enables the metal pattern to function as a hillock formation start point, and (4) maintains electrical isolation. This multi-functionality justifies the additional layer by providing multiple benefits within a single structural element.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design results in a uniform TFT characteristic by uniformly arranging hillocks around the metal pattern, reducing deviations in threshold voltage, operation voltage distribution, and hysteresis, thereby improving the overall performance and reducing defects like weak bright points.
Implementation Method 1
In a crystallization process of polysilicon, a hillock is formed in a polysilicon layer surface
Data Source
AI summary
A thin film transistor array panel according to an exemplary embodiment includes: a substrate; a metal pattern positioned on the substrate; a buffer layer positioned on the metal pattern; and a semiconductor layer positioned on the buffer layer and including a source region, a channel region, and a drain region, wherein the metal pattern overlaps at least one of the source region and the drain region, and the metal pattern does not overlap the channel region.