Thin-Film Transistor Array with LDD Gate Control for Leakage Suppression
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Solution Overview
Problem
Existing thin film transistor arrays in display devices face challenges in reducing leakage current and improving reliability, particularly when the transistors are turned off, due to the lack of effective control over the lightly doped drain (LDD) regions.
Innovation Solution
The proposed solution involves a thin film transistor array panel design with a semiconductor layer having a channel region, source region, and drain region, along with control gate electrodes that independently control the LDD regions to prevent leakage current by applying specific voltage configurations, ensuring that the channel is disconnected when the transistor is turned off.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional thin film transistor design is used without control gate electrodes over LDD regions, then device complexity is reduced, but leakage current increases and reliability deteriorates
Solution Approach 1:
The gate electrode structure is segmented into multiple independent control gates: a first control gate electrode positioned over the LDD region and a second control gate electrode positioned over the channel region. This segmentation allows independent voltage control of different transistor regions, enabling effective leakage current suppression through the first control gate while maintaining proper transistor operation through the second control gate, thereby improving reliability without excessive complexity.
Solution Approach 2:
Different control mechanisms are applied to different regions of the transistor. The first control gate electrode provides localized control over the LDD region to suppress leakage current, while the second control gate electrode controls the channel region for normal transistor operation. This local quality approach targets the specific problem area (LDD region) without affecting other functional regions, improving reliability with minimal added complexity.
2Object-generated harmful factors
If control gate electrodes are added to independently control LDD regions, then leakage current is reduced, but device complexity increases
Solution Approach 1:
The control function is segmented between two specialized gate electrodes: the first control gate electrode specifically controls the LDD region to prevent leakage current, while the second control gate electrode controls the channel region for standard transistor operation. This segmentation enables targeted leakage suppression without requiring complete redesign of the entire gate structure, reducing the harmful effect while limiting the increase in complexity.
Solution Approach 2:
The first control gate electrode acts as an intermediary element between the control circuitry and the LDD region, providing voltage control to suppress leakage current. This intermediary structure enables effective leakage current reduction through electrical control without requiring physical modification of the LDD region itself, achieving harm reduction with manageable structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces leakage current and enhances the reliability of the thin film transistors by ensuring that the channel is disconnected during the off-state, thereby improving the overall performance and characteristics of the transistors.
Implementation Method 1
control gate electrodes that independently control the LDD regions to prevent leakage current by applying specific voltage configurations
Data Source
AI summary
A thin film transistor array panel includes a substrate, a first gate electrode on the substrate, a semiconductor layer on the first gate electrode, the semiconductor layer including a drain region, a source region, a lightly doped drain (LDD) region, and a channel region, a second gate electrode on the semiconductor layer, the first gate electrode and the second gate electrode each overlapping the channel region, a control gate electrode that overlaps the LDD region, and a source electrode and a drain electrode respectively connected with the source region and the drain region of the semiconductor layer.