Thin Film Transistor Array Three-Round Mask Process
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Solution Overview
Problem
The manufacturing process of thin film transistor array substrates for liquid crystal display devices is complex and costly due to the multiple mask processes involved, limiting further reductions in manufacturing costs.
Innovation Solution
A method for manufacturing a thin film transistor array substrate using a three-round mask process, which simplifies the process by integrating the formation of gate lines, semiconductor patterns, and passivation films, and includes a lift-off method for forming the pixel electrode, reducing the number of mask processes and manufacturing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a four-round mask process is used to reduce manufacturing steps, then the number of mask processes is reduced from five, but the manufacturing process remains complex and costly
Solution Approach 1:
The patent combines multiple process steps into fewer mask rounds. Specifically, it merges the formation of gate lines, data lines, and pixel electrodes into integrated patterning steps, and combines passivation film formation with electrode formation in the same mask process, thereby reducing the total number of mask processes while simplifying the overall manufacturing flow
Solution Approach 2:
The patent designs mask patterns that serve multiple functions simultaneously. For example, a single mask pattern is used to define both the pixel electrode regions and the openings in the passivation layer, and another mask pattern simultaneously forms both gate lines and data lines, making each mask process multi-functional and reducing the total number of required mask rounds
2Manufacturing precision
If multiple mask processes are used to form gate lines, data lines, and pixel electrodes separately, then each component can be precisely controlled, but the manufacturing cost and process time increase
Solution Approach 1:
The patent merges the patterning of gate lines, data lines, and pixel electrodes into combined mask processes. The first mask process simultaneously patterns gate lines and data lines, while the second mask process simultaneously patterns pixel electrodes and passivation layer openings, maintaining precision through integrated design while improving productivity
Solution Approach 2:
The patent performs preliminary patterning of conductive layers before final electrode formation. The gate and data lines are pre-formed in the first mask process, establishing the transistor structure beforehand, which allows the pixel electrodes to be formed in subsequent steps without requiring separate mask processes for each component
Data Source
AI summary
A method of manufacturing a thin film transistor array substrate includes: forming a gate pattern on a substrate; forming a first gate insulating film and a second gate insulating film on the substrate; forming a source/drain pattern and a semiconductor pattern on the substrate; forming a passivation film on the substrate; forming a photo-resist pattern on the passivation film; patterning the passivation film using the photo-resist pattern to form a passivation film pattern, the patterning of the passivation film including over-etching the passivation film to form an open region in the passivation film; forming a transparent electrode film on the substrate; removing the photo-resist pattern and a portion of the transparent electrode film on the photo-resist pattern; and forming a pixel electrode on the first gate insulating layer.