Thin Film Transistor Array Panel Light Leakage Prevention

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Solution Overview

Problem

Conventional LCD manufacturing methods result in light leakage due to misalignment between gate and data lines, leading to reduced aperture ratios and light transmittance, as well as increased parasitic capacitance causing signal delay.

Innovation Solution

The implementation of a thin film transistor array panel design with strategically positioned light blocking members on opposite sides of data lines, overlapping them with specific widths and intervals to minimize parasitic capacitance and prevent light leakage, while maintaining a high aperture ratio and misalignment margin.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the area of the light blocking member is made sufficiently wide to accommodate misalignment margin, then light leakage is prevented, but the aperture ratio and light transmittance are diminished

Engineering Contradiction:
Improvelight leakage preventionVSAvoidaperture ratio
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The light blocking member is divided into multiple segments: a first light blocking member extending from the gate line, a second light blocking member extending from the data line, and a third light blocking member connecting them. This segmentation allows each segment to be optimized for specific functions - the first two provide misalignment coverage while the third minimizes capacitance by being positioned away from the data line edge.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different portions of the light blocking structure have different properties. The first and second light blocking members have larger dimensions to ensure misalignment coverage, while the third light blocking member has minimized dimensions and specific positioning to reduce parasitic capacitance. This local optimization resolves the contradiction between coverage area and capacitance reduction.

Inventive Principle:
Principle #3Local quality

2Loss of time

If the light blocking member is positioned to minimize parasitic capacitance, then signal delay is reduced, but light leakage may occur due to misalignment

Engineering Contradiction:
Improvesignal delayVSAvoidlight leakage prevention
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The first light blocking member extends from the gate line toward the data line in advance, creating a preliminary barrier that covers potential misalignment ranges. The second light blocking member similarly extends from the data line. This preliminary positioning ensures that even if alignment is imperfect, the light blocking members are already in position to prevent leakage.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The third light blocking member acts as an intermediary connection between the first and second light blocking members. It provides the necessary structural connection to maintain electrical isolation while allowing the first two members to be positioned optimally for both misalignment coverage and capacitance reduction.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Area of stationary object

If the interval between light blocking members is reduced to increase aperture ratio, then light transmittance is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improvelight transmittanceVSAvoidalignment precision
Core Design Contradiction:
Area of stationary objectVSManufacturing precision

Solution Approach 1:

The first and second light blocking members extend beyond the immediate gap area, creating a cushioning effect that compensates for potential manufacturing variations. Their extended positioning ensures that even if there are slight deviations in the interval between members, the light blocking function is maintained, thus cushioning against precision errors.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS8203674B2Manufacturing thin film transistor array panels for flat panel displays
Publication Date: 2012.06.19 SAMSUNG DISPLAY CO LTD
  • US8203674B2 patent drawing
  • US8203674B2 patent drawing
  • US8203674B2 patent drawing

AI summary

A thin film transistor array panel for a flat panel display includes a substrate, a first signal line formed on the substrate, a second signal line intersecting and insulated from the first signal line, a switching element having a first terminal connected to the first signal line, a second terminal connected to the second signal line, and a third terminal, a pixel electrode connected to the third terminal of the switching element, and first and second light blocking members extending parallel to the second signal line, each being disposed on an opposite side of and partially overlapping an respective edge of the second signal line, an interval between the first and second light blocking members being in a range of from more than 1.5 μm to less than 4 μm. The array panel prevents light leakage from the display and improves its transmittance, aperture ratio and color reproducibility.