TFT Array Substrate Structure for Low Capacitance OLED Displays

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Solution Overview

Problem

Existing thin film transistor array substrates for organic light-emitting display apparatuses face challenges with parasitic capacitance, off-state leakage current, and reduced on-state current, which affect display quality and efficiency.

Innovation Solution

The implementation of a thin film transistor structure that includes a first and second silicon active layer with an oxide active layer in between, a gate electrode with a gate insulating layer, and source and drain electrodes with an interlayer insulating layer, where the regions of the silicon active layers not overlapping the gate electrode are doped with N+ or P+ ion impurities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional thin film transistor structure is used, then the device can be manufactured with standard processes, but parasitic capacitance increases and on-state current decreases

Engineering Contradiction:
Improveparasitic capacitanceVSAvoidon-state current
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The active layer is segmented into multiple layers (first active layer, second active layer, and oxide active layer) with different materials and doping configurations. This segmentation allows optimization of different regions: the oxide active layer reduces parasitic capacitance while the doped silicon regions maintain high on-state current, resolving the contradiction between these two parameters.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the active layer are assigned different local qualities through selective doping. The first and second active layers are doped with N+ or P+ ion impurities in regions not overlapping the gate electrode, creating high-conductivity source/drain regions. The oxide active layer region maintains low parasitic capacitance. This local differentiation simultaneously achieves low parasitic capacitance and high on-state current.

Inventive Principle:
Principle #3Local quality

2Productivity

If the active layer is doped to increase on-state current, then current flow improves, but off-state leakage current increases

Engineering Contradiction:
Improveon-state currentVSAvoidoff-state leakage current
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

Doping is applied locally only to specific regions of the first and second active layers (regions not overlapping the gate electrode), while the oxide active layer region remains undoped or lightly doped. This local quality differentiation allows high on-state current through doped source/drain regions while maintaining low off-state leakage current through the undoped oxide channel region.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The oxide active layer acts as an intermediary between the doped silicon active layers. It provides a low-parasitic-capacitance channel that prevents leakage current while allowing the doped silicon regions to provide high current drive capability, thus mediating between the conflicting requirements of high on-state current and low off-state leakage.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of manufacture

If a simple active layer structure is used, then manufacturing is easier, but device characteristics deteriorate

Engineering Contradiction:
Improvestructure complexityVSAvoiddevice characteristics
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The active layer is segmented into three distinct layers (first active layer, second active layer, oxide active layer) that can be formed using standard thin film deposition and patterning processes. While the structure is more complex than a single-layer active layer, each layer can be manufactured using conventional techniques, maintaining ease of manufacture while achieving superior device characteristics through the multi-layer configuration.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The active layer uses a composite structure combining different materials (silicon-based first and second active layers with oxide-based active layer). This composite material approach enables simultaneous achievement of high mobility (from silicon), low parasitic capacitance (from oxide), and good interface properties, improving device characteristics while remaining compatible with existing manufacturing processes.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration decreases parasitic capacitance, increases the on-state current, and reduces off-state leakage current, resulting in improved device characteristics and display quality for large-sized and high-resolution organic light-emitting display apparatuses.

Implementation Method 1

an oxide active layer in a space between the first silicon active layer and the second silicon active layer

Methodology Applied
Scientific EffectParasitic capacitance reduction: Capacitance

Implementation Method 2

Regions of the first silicon active layer and the second silicon active layer that do not overlap the gate electrode may be doped with N+ or P+ ion impurities

Methodology Applied
Scientific EffectIon doping: Ion Implantation

Data Source

PatentUS12288823B2Thin film transistor array substrate, organic light-emitting display apparatus, and method of manufacturing the thin film transistor array substrate
Publication Date: 2025.04.29 SAMSUNG DISPLAY CO LTD
  • US12288823B2 patent drawing
  • US12288823B2 patent drawing
  • US12288823B2 patent drawing

AI summary

Provided is a thin film transistor including an active layer including a first silicon active layer, a second silicon active layer, and an oxide active layer in a space between the first silicon active layer and the second silicon active layer, a gate electrode on the active layer with a gate insulating layer disposed therebetween, and a source electrode and a drain electrode with an interlayer insulating layer disposed between the gate electrode and the source and drain electrodes, the source and drain electrodes being in contact with the first silicon active layer and the second silicon active layer, respectively.