Thin Film Transistor Array Substrate Mask Process Reduction
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Solution Overview
Problem
Conventional thin film transistor array substrate manufacturing processes are complex and costly due to the need for multiple mask exposure steps, increasing production time and costs.
Innovation Solution
A method that simplifies the process by forming a gate electrode and line, active layer, source and drain electrodes, and passivation layers with fewer exposure steps, using a gate insulating layer, organic insulating layer, and multiple passivation layers to define pixel and common electrode patterns with a single etching process, reducing the number of mask processes and manufacturing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple mask exposure steps are used to form gate line, gate electrode, active layer, etching stop layer, source electrode, drain electrode, passivation layer, electrode and vias, then the thin film transistor array substrate can be manufactured with conventional FFS type, but the production process becomes complicated and manufacturing cost increases
Solution Approach 1:
The patent combines multiple separate mask exposure steps into a single integrated process. Specifically, the gate line, gate electrode, active layer, source electrode, and drain electrode are formed simultaneously using one mask pattern, and the pixel electrode and common electrode are formed in the same exposure step, reducing the total number of mask processes from 6-8 times to just 2 times while maintaining transistor quality
Solution Approach 2:
The single mask pattern serves multiple functions by simultaneously defining the gate line, gate electrode, active layer, source electrode, and drain electrode regions. The same mask layer is used to pattern all these components, making the mask process universal rather than requiring separate specialized masks for each component
2Reliability
If multiple mask exposure steps are used to form all layers and electrodes, then complete thin film transistor structure can be achieved, but exposure time increases and production efficiency decreases
Solution Approach 1:
The patent merges multiple exposure operations into two consolidated exposure steps. The first exposure forms the transistor structure (gate line, gate electrode, active layer, source electrode, drain electrode), and the second exposure forms the electrode structure (pixel electrode, common electrode, via holes). This consolidation reduces total exposure time and increases production throughput while maintaining structural completeness
Solution Approach 2:
The mask pattern is designed in advance to pre-define all necessary regions for both the transistor structure and electrode structure. The photoresist layer is applied and patterned beforehand to create a comprehensive mask that guides the formation of multiple components in a single exposure, eliminating the need for sequential exposure operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of mask processes required, simplifies the manufacturing process, and decreases production costs while maintaining the quality of the thin film transistor array substrate.
Implementation Method 1
adding a second dry etching gas and etching the region of the organic insulating layer exposed by the second passivation layer
Implementation Method 2
using a first dry etching gas to etch the second passivation layer, the organic insulating layer, the first passivation layer and partial of the gate insulating layer, and adding a second dry etching gas and etching the region of the organic insulating layer exposed by the second passivation layer. Wherein the second etching gas and the first and the etching gas are the same or are oxygen.
Implementation Method 3
ashing the photoresist layer
Implementation Method 4
depositing a conductive layer material on the defined second passivation layer and the region of the organic insulating layer exposed by the second passivation layer
Data Source
AI summary
The present application discloses a method for manufacturing a thin film transistor, including: subsequently depositing a first passivation layer, an organic insulating layer, and a second passivation layer on a gate insulating layer of the substrate, an active layer, a source electrode and a drain electrode; applying a photoresist layer on the second passivation layer, and performing a pattern process to define a pixel electrode layer pattern, a common electrode layer pattern, and a cured layer pattern; defining the pixel electrode layer pattern, the common electrode layer pattern, and the cured layer pattern by the etching process on the second passivation layer, the organic insulating layer, the first passivation layer and partial of the gate insulating layer, ashing the photoresist layer; and forming a pixel electrode layer on the organic insulating layer, forming a common electrode layer on the organic insulating layer exposed by the second passivation layer.