TFT Array Substrate with MIM Capacitor Etch Stop
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Solution Overview
Problem
The existing manufacturing processes for thin film transistor array substrates and organic light-emitting display devices are complex and costly, requiring multiple mask processes, which can lead to increased costs and potential issues like current leakage in the capacitor region.
Innovation Solution
A method involving five mask processes is developed to manufacture a thin film transistor array substrate with a bottom gate type TFT, utilizing crystalline silicon for the active layer and amorphous silicon with ion impurities for the source and drain electrodes, and a metal-insulator-metal (MIM) capacitor structure with an ion impurity-doped upper electrode as an etch stop layer, reducing contact resistance and enhancing electrical capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple mask processes are used to form fine patterns, then manufacturing precision is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines the gate electrode and lower electrode into the same layer, and merges the formation of multiple electrodes into a single mask process. This reduces the number of separate mask processes required while maintaining the precision of fine pattern formation, directly addressing the contradiction between manufacturing precision and process complexity
Solution Approach 2:
The gate electrode and lower electrode are designed to serve multiple functions within the same structural layer. This multi-functionality allows a single mask process to define both electrodes, reducing the overall number of masking steps required in the manufacturing process while maintaining pattern precision
2Manufacturing precision
If multiple mask processes are used to form fine patterns, then manufacturing precision is improved, but manufacturing cost increases
Solution Approach 1:
By merging the gate electrode and lower electrode formation into a single mask process, the patent reduces the total number of mask processes required. This consolidation directly lowers manufacturing costs while maintaining the necessary fine pattern precision through the unified masking approach
3Device complexity
If conventional capacitor structure is used, then device complexity is reduced, but current leakage occurs in capacitor region
Solution Approach 1:
The upper electrode of the capacitor is constructed as a composite structure with a first layer made of the same material as the active layer and a second layer made of the same material as the source and drain electrodes. This composite material structure provides both electrical functionality and prevents current leakage in the capacitor region
4Reliability
If ion impurity-containing amorphous silicon is used for source and drain electrodes, then contact resistance is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the material parameters of the source and drain electrodes by using ion impurity-containing amorphous silicon instead of conventional materials. This parameter change reduces contact resistance while the unified mask process maintains the necessary pattern formation precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, reduces contact resistance, and increases the electrical capacity of the capacitor, while minimizing the risk of current leakage, thereby improving the efficiency and reliability of the organic light-emitting display device.
Implementation Method 1
an upper electrode on the first insulating layer, the upper electrode including a first layer made of a same material as the active layer, and a second layer made of a same material as the source and drain electrodes
Implementation Method 2
ion impurity-containing amorphous silicon
Data Source
AI summary
A thin film transistor array substrate includes a thin film transistor including a gate electrode, an active layer, and source and drain electrodes, a pixel electrode on a same layer as the gate electrode, a lower electrode of a capacitor, the lower electrode being on the same layer as the gate electrode, a first insulating layer on the gate electrode and the lower electrode, a second insulating layer between the active layer and the source and drain electrodes, an upper electrode on the first insulating layer, the upper electrode including a first layer made of a same material as the active layer, and a second layer made of a same material as the source and drain electrodes, and a third insulating layer that covers the source and drain electrodes and the upper electrode and exposes the pixel electrode.