Thin Film Transistor Array Panel Mold Layer Through-Holes
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Solution Overview
Problem
The existing solution processes for manufacturing thin film transistors require additional steps for forming banks to seal the semiconductor, which complicates the production of large flat panel displays and is not efficiently compatible with conventional deposition processes.
Innovation Solution
A thin film transistor array panel is developed using an organic semiconductor with a manufacturing method that includes a gate line, gate insulating layer, mold layer, data line, passivation layer, and pixel electrode, featuring through-holes for semiconductor filling, and utilizing Inkjet printing to prevent damage to the organic semiconductor, allowing for efficient production without additional sealing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a solution process is used to manufacture semiconductor, then it can be easily applied to large flat panel displays, but it requires an additional process for forming a bank for sealing the solution
Solution Approach 1:
The patent extracts and eliminates the bank formation process from the semiconductor manufacturing sequence. By directly forming the semiconductor layer on the substrate without preliminary bank structures, the invention removes the sealing step while maintaining solution process advantages, thereby reducing process complexity while preserving ease of manufacture for large displays
Solution Approach 2:
The invention performs preliminary preparation of the substrate surface and gate electrode structure before semiconductor deposition, ensuring that the semiconductor can be directly formed without subsequent sealing requirements. This preliminary structuring eliminates the need for bank formation while maintaining process simplicity
2Device complexity
If a conventional deposition process is used, then the process is simple, but it is limited for large flat panel displays
Solution Approach 1:
The patent replaces conventional vacuum deposition mechanisms with solution-based deposition methods. This substitution enables manufacturing on large substrate areas while maintaining process simplicity, as solution processes can be applied using techniques like spin coating, dip coating, or inkjet printing that are not constrained by vacuum chamber size limitations
Solution Approach 2:
The invention changes the deposition parameters from vacuum-based physical vapor deposition to solution-based chemical deposition. This parameter change allows for scalable processing on large substrates while keeping the overall process simple and compatible with existing manufacturing infrastructure
3Reliability
If through-holes are formed in passivation layer and electrodes, then semiconductor can be filled and protected, but additional processing steps are required
Solution Approach 1:
The patent merges the through-hole formation with the pixel electrode patterning process. The same photolithography and etching steps that define the pixel electrodes also create the through-holes, eliminating separate processing steps while ensuring proper semiconductor filling and protection regions
Solution Approach 2:
The through-holes serve multiple functions: they define the pixel electrode boundaries, provide pathways for semiconductor material deposition, and create protection structures. This multi-functionality reduces the number of required processing steps while maintaining reliable semiconductor protection
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the production of thin film transistor array panels by integrating an organic semiconductor, reducing complexity and enhancing efficiency, while ensuring the semiconductor is protected from damage during processing.
Implementation Method 1
utilizing Inkjet printing to prevent damage to the organic semiconductor
Data Source
AI summary
A thin film transistor array panel according to the present invention includes: a gate line formed on a substrate and including a gate electrode; a gate insulating layer formed on the gate electrode; a mold layer formed on the gate insulating layer and having an opening overlapping the gate electrode; a semiconductor layer filled in the opening; a data line formed on the mold layer and including a source electrode contacted with the semiconductor layer; a drain electrode contacted with the semiconductor layer on the mold layer and facing the source electrode; a passivation layer formed on the data line and the drain electrode; and a pixel electrode formed on the passivation layer and connected to the drain electrode, wherein the passivation layer, the source electrode, and the drain electrode have at least one through-hole connected to the opening.