Thin Film Transistor Array Substrate Multi-Tone Mask Patterning
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Solution Overview
Problem
The manufacturing process for thin film transistor array substrates in liquid crystal displays is complex and costly due to the requirement of multiple masks, leading to increased production difficulties and expenses.
Innovation Solution
A method involving the use of a multi-tone mask, chemical vapor deposition, and specific etching processes to form a thin film transistor array substrate with fewer masks, reducing the complexity and cost of the manufacturing process by sequentially depositing and patterning layers using a transparent conductive layer, metal layers, and a planarization layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple masks are used in the manufacturing process, then the thin film transistor array substrate can be formed with traditional methods, but the manufacturing cost increases and the process becomes complex
Solution Approach 1:
The patent combines the functions of multiple masks into a single multi-layer mask structure. The mask includes a first mask layer and a second mask layer that work together to define both the gate electrode pattern and the source/drain electrode pattern in one exposure step, eliminating the need for separate exposure steps with individual masks.
Solution Approach 2:
The mask is segmented into multiple functional layers, where the first mask layer defines one set of patterns and the second mask layer defines another set of patterns. This segmentation allows different pattern definitions within a single mask structure, enabling complex patterning without multiple separate masks.
2Reliability
If multiple masks are used in the manufacturing process, then the thin film transistor array substrate can be formed with traditional methods, but the manufacturing cost increases
Solution Approach 1:
The patent combines the functions of multiple masks into a single multi-layer mask structure. The mask includes a first mask layer and a second mask layer that work together to define both the gate electrode pattern and the source/drain electrode pattern in one exposure step, eliminating the need for separate exposure steps with individual masks.
3Reliability
If multiple masks are used in the manufacturing process, then the thin film transistor array substrate can be formed with traditional methods, but the production time increases
Solution Approach 1:
The patent combines the functions of multiple masks into a single multi-layer mask structure. The mask includes a first mask layer and a second mask layer that work together to define both the gate electrode pattern and the source/drain electrode pattern in one exposure step, eliminating the need for separate exposure steps with individual masks.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method simplifies the manufacturing process, reduces costs, and enhances production efficiency by utilizing a three-mask process instead of the traditional four-mask process, thereby improving the production of liquid crystal displays.
Implementation Method 1
depositing sequentially a transparent conductive layer and a first metal layer on the substrate by a sputtering process
Implementation Method 2
the gate insulative layer and the semi-conductive layer are sequentially deposited by chemical vapor deposition method
Data Source
AI summary
The present invention discloses a thin film transistor array substrate and a manufacturing method for the same. A transparent conductive layer and a first metal layer are deposited on a substrate, and a multi-tone mask is utilized to form a gate electrode and a common electrode. A gate insulative layer and a semi-conductive layer are deposited on the substrate with the gate electrode and the common electrode, and the semi-conductive layer is patterned by a second mask to retain a region of the semi-conductive layer that is there-above the gate electrode. A second metal layer is deposited on the substrate with the gate insulative layer along with the retained semi-conductive layer, and the second metal layer is patterned by a third mask to form a source electrode, a drain electrode, and a pixel electrode. The present invention provides a simple manufacturing method.