Thin Film Transistor Array Panel With Nano Particles
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Solution Overview
Problem
Conventional thin film transistor arrays face challenges with low electron mobility due to amorphous silicon, and oxide semiconductors suffer from changes in carrier concentration and uniformity issues, leading to performance variations and instability.
Innovation Solution
Incorporating nano particles with diameters between 2 nm to 5 nm, made of metals or their oxides, dispersed on or within the semiconductor layer, to stabilize carrier concentration and maintain performance characteristics regardless of external effects or manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If amorphous silicon is used as the active layer, then the manufacturing process is simple, but the electron mobility is low and high-speed driving cannot be effectively performed
Solution Approach 1:
The patent uses low-temperature polysilicon as a composite material that combines the ease of manufacturing associated with silicon-based materials with improved electron mobility characteristics, resolving the contradiction between manufacturing simplicity and high-speed performance
2Speed
If low-temperature polysilicon or oxide semiconductor is used to implement high electron mobility, then the electron mobility improves, but the processing procedure becomes complicated and uniformity of the semiconductor layer cannot be effectively secured
Solution Approach 1:
The patent optimizes specific parameters including crystalline phase composition (containing crystalline silicon phase), carrier concentration (10^19 to 10^21 cm^-3), and thickness (50-200 nm) to achieve both high electron mobility and manufacturing uniformity
3Ease of manufacture
If oxide semiconductor is deposited by PVD method or coating process, then the manufacturing cost is reduced, but the carrier concentration changes greatly based on external effects such as oxygen and water
Solution Approach 1:
The patent employs an inert atmosphere environment during deposition and processing to prevent oxidation and water contamination of the oxide semiconductor, thereby maintaining stable carrier concentration while using cost-effective deposition methods
Solution Approach 2:
The patent uses composite oxide semiconductor materials such as IGZO (Indium Gallium Zinc Oxide) that inherently provide stable electrical characteristics and resistance to external environmental effects while maintaining compatibility with low-cost manufacturing processes
4Ease of manufacture
If oxide semiconductor is laminated, then the film formation is facilitated, but the thickness uniformity is lowered during solution process and the characteristic of the thin film transistor changes
Solution Approach 1:
The patent controls the thickness of each laminated oxide semiconductor layer within specific ranges (50-200 nm per layer) and optimizes the number of layers to achieve both ease of film formation through lamination and sufficient thickness uniformity to prevent characteristic variations
Data Source
AI summary
A thin film transistor array panel includes: a substrate; a gate electrode disposed on the substrate; a semiconductor layer disposed on the substrate and overlapping the gate electrode; a plurality of nano particles disposed on or in the semiconductor layer; a source electrode disposed on the substrate; and a drain electrode disposed on the substrate, where the source electrode and the drain electrode are spaced apart from each other, and the semiconductor layer is disposed between the source electrode and the drain electrode, in which a diameter of each of the nano particles is in a range of about 2 nm to about 5 nm, or a ratio of a plane area of the nano particles per unit area of the semiconductor layer is in a range of about 5% to about 80%.