TFT Array Node Contact Layout for Larger Pixel Capacitor Area
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Solution Overview
Problem
Current display devices face challenges in achieving efficient space arrangement and high resolution due to complex connections between thin-film transistors (TFTs), capacitors, and wires, which restricts the design margin and area utilization for capacitors.
Innovation Solution
The proposed solution integrates two TFTs and one capacitor in a pixel with a unified node contact hole, eliminating the need for an insulation bank between contact holes, thereby maximizing space utilization and allowing for a larger capacitor area, enhancing high resolution pixel design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate contact holes with insulation banks are used for connecting TFTs and capacitors, then electrical insulation is ensured, but space utilization is reduced and design margin is restricted
Solution Approach 1:
The patent merges multiple separate contact holes into a single unified contact hole structure. Specifically, the first contact hole and second contact hole are combined into one contact hole that exposes both the first electrode and second electrode, eliminating the need for separate insulation banks between them. This merging approach maintains electrical insulation through the layered structure while maximizing the capacitor area by removing redundant insulation elements.
Solution Approach 2:
The patent extracts and eliminates the insulation bank structure from the design. By removing the insulation bank that would traditionally be placed between separate contact holes, the design achieves space optimization. The electrical insulation function is maintained through the inherent insulation properties of the layered structure (gate insulating layer, interlayer insulating layer) rather than requiring additional insulation banks.
2Reliability
If complex connection structures with multiple insulation layers are used, then electrical isolation is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple contact holes and their associated insulation banks into a single unified contact hole structure. This reduces the number of discrete components and simplifies the overall connection structure. The electrical isolation is maintained through the existing gate insulating layer and interlayer insulating layer that are integral parts of the TFT structure, rather than requiring additional separate insulation elements.
Solution Approach 2:
The unified contact hole structure serves multiple functions simultaneously: it provides electrical connection for both the first electrode and second electrode, maintains electrical isolation through the layered insulating structure, and maximizes the capacitor area. This multi-functional design eliminates the need for separate specialized components for each function.
Data Source
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AI summary
A thin-film transistor (TFT) array substrate including: a first conductive layer selected from an active layer, a gate electrode, a source electrode, and a drain electrode of a TFT; a second conductive layer in a layer different from the first conductive layer; and a connection node coupling the first conductive layer to the second conductive layer. Here, the TFT array has a node contact hole formed by: a first contact hole in the first conductive layer; and a second contact hole in the second conductive layer, the second contact hole being integral with the first contact hole and not being separated from the first contact hole by an insulating layer, and at least a portion of the connection node is in the node contact hole.