Thin Film Transistor Array Panel Overlapping Area Consistency

The patent changes the geometric parameters of the gate electrode and source/drain electrode to create an overlapping region configuration that compensates for mask misalignment. Specifically, the gate electrode is designed with extended portions that overlap the source/drain electrodes, and the source/drain electrodes are configured with specific widths and positions so that even when masks are misaligned, the total overlapping area remains substantially constant. This parameter optimization ensures that the parasitic capacitance formed by the overlapping regions remains stable despite manufacturing variations.

The patent applies local quality by designing different overlapping configurations for different regions of the zigzag arrangement. In regions where the zigzag pattern causes increased overlap, the electrode dimensions are adjusted to reduce overlap elsewhere, maintaining uniform total overlapping area. The gate electrodes and source/drain electrodes are locally optimized in each zigzag segment to ensure consistent parasitic capacitance across the entire display panel, preventing striped patterns while preserving space utilization benefits.

The patent applies partial action by forming overlapping regions only where necessary to achieve stable parasitic capacitance, rather than maximizing overlap throughout. The gate electrode overlaps the source/drain electrodes in specific controlled regions, providing sufficient parasitic capacitance for stable operation without excessive overlap that would reduce visibility and viewing angles. This optimized partial overlapping configuration achieves the right balance between electrical performance and optical quality.